AT90USB646 datasheet(34/456 Pages) ATMEL

34 / 456 page

7593L–AVR–09/12

AT90USB64/128

Note:

1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or

SRW00 (lower sector). The ALE pulse in period T4 is only present if the next instruction

accesses the RAM (internal or external).

Figure 6-7.

External data memory cycles with SRWn1 = 0 and SRWn0 = 1

(1).

Note:

1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or

SRW00 (lower sector).

The ALE pulse in period T5 is only present if the next instruction accesses the RAM (internal

or external).

Figure 6-8.

External data memory cycles with SRWn1 = 1 and SRWn0 = 0 (1).

Note:

1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or

SRW00 (lower sector).

The ALE pulse in period T6 is only present if the next instruction accesses the RAM (internal

or external).

ALE

A15:8

Address

Prev. addr.

DA7:0

Address

Data

Prev. data

DA7:0 (XMBK = 0)

Data

Prev. data

Address

Data

Prev. data

Address

DA7:0 (XMBK = 1)

System clock (CLK CPU)

ALE

A15:8

Address

Prev. addr.

DA7:0

Address

Data

Prev. data

DA7:0 (XMBK = 0)

Data

Prev. data

Address

Data

Prev. data

Address

DA7:0 (XMBK = 1)

System clock (CLK CPU)

AT90USB646 Datasheet(PDF) 34 Page - ATMEL Corporation

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