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APW7066 Datasheet(PDF) 29 Page - Anpec Electronics Coropration |
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APW7066 Datasheet(HTML) 29 Page - Anpec Electronics Coropration |
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29 / 35 page ![]() Copyright © ANPEC Electronics Corp. Rev. A.8 - Aug., 2009 APW7066 www.anpec.com.tw 29 Figure 15. Layout Guidelines Layout Consideration Application Information (Cont.) • The input capacitor should be near the drain of the up- per MOSFET; the output capacitor should be near the loads. The input capacitor GND should be close to the output capacitor GND and the lower MOSFET GND. • The drain of the MOSFETs (VIN and phase nodes) should be a large plane for heat sinking. V IN V OUT Q1 L1 C IN APW7066 L O A D BOOT VCC12 SS FB GND C SS C VCC C BOOT Q2 C OUT VCC LG UG PGND C VCC12 VREF C VREF REFOUT C REFOUT |
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