Copyright

© ANPEC Electronics Corp.

Rev. A.4 - Jan., 2013

www.anpec.com.tw

13

APA3160

Function Description (Cont.)

Left-Justified

Left-justified (LJ) timing uses LRCLK to define the data for the left channel and the right channel when the data being

transmitted. For the left channel, the LRCLK is high; for the right channel, the LRCLK is low. A bit clock running at 32,

48, or 64 × f

is written MSB first and is valid on the rising edge of the bit clock. The DAP masks unused trailing data bit positions.

Figure 4. Left-Justified 64 f

Figure 5. Left-Justified 48 f

Figure 6. Left-Justified 32 f

23

22

9

8

5

4

1

0

19 18

5

4

1

0

15 14

1

0

23 22

9

8

5

4

1

0

19 18

5

4

1

0

15 14

1

0

32Clks

32Clks

LRCLK

Left Channel

Right Channel

SCLK

SCLK

MSB

MSB

LSB

LSB

24-Bit Mode

20-Bit Mode

16-Bit Mode

24-Bit Mode

20-Bit Mode

16-Bit Mode

23

22

17

16

9

8

5

4

19

18

13 12

5

4

15

14

9

8

24Clks

24 Clks

LRCLK

Left Channel

Right Channel

SCLK

SCLK

MSB

LSB

LSB

24-Bit Mode

20-Bit Mode

16-Bit Mode

1

0

1

0

3

2

1

0

23 22

17 16

9

8

5

4

19 18

13

12

5

4

15 14

9

8

MSB

24-Bit Mode

20-Bit Mode

16-Bit Mode

1

0

1

0

3

2

1

15 14

12 11

9

8

5

4

16 Clks

16Clks

LRCLK

Left Channel

Right Channel

SCLK

SCLK

MSB

LSB

LSB

16-Bit Mode

3

2

1

0

MSB

16-Bit Mode

13

10

15 14

12

11

9

8

5

4

3

2

1

13

10

0