AD9726-EBZ datasheet(22/24 Pages) AD

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AD9726

Rev. B | Page 22 of 24

and the SELFCAL bit is cleared. Following the cycle, the device

reports a self-calibrated state (CALMEM = 01b).

As with MEMXFER, successful assertion of the SELFCAL bit

(Bit 6 in Register 0x0F)requires that Bits[3:0] in Register 0x0F

be clear. If any of these bits are asserted (such that an

SMEM/FMEM read/write/clear state is enabled), the self-

calibration cycle does not begin.

The time required to self-calibrate is dependent on both the

DAC clock frequency and the value of CALCLK (Bits[5:0] in

than ordinary operation, the DAC clock is divided into a slower

version and used to step through the process. Time made

available to the self-calibration algorithm directly impacts its

ability to provide accurate results.

A maximum fixed division ratio (4096) corresponds to the

minimum default value of CALCLK (0). The division ratio can

be decreased by increasing the value of CALCLK. Each increase

in the value of CALCLK reduces the DAC clock division factor

(and, therefore, the time made available to self-calibration) by

50%. With CALCLK at its maximum value (7), the divide ratio

declines to its minimum value (32).

With CALCLK at its default value, self-calibration requires

approximately 100 ms at a DAC clock frequency of 100 MHz.

This time can be reduced to under 0.8 ms if CALCLK = 7. Time

scales relative to DAC clock frequency.

Performance Effects of Calibration

Harmonic distortion for low frequency outputs is primarily a

function of DAC linearity. Figure 12 to Figure 14 show the

harmonic distortion performance of the AD9726.

Figure 12 shows a 1 MHz full-scale output tone. The output

drives a unique low-pass and high-pass filter called a diplexer.

This type of filter presents a uniform 50 Ω load to the DAC and

splits the output signal into low and high frequency paths. The

diplexer's low-pass output passes the 1 MHz fundamental but

attenuates higher frequencies, and the diplexer's high-pass out-

put passes higher frequencies and attenuates the 1 MHz funda-

mental. Figure 12 also shows the diplexer's low-pass output.

Here the noise floor is higher than the harmonic distortion

because with a high power input signal, attenuation is required

by the spectrum analyzer.

Figure 13 shows the diplexer's high pass output where the

attenuated input signal can be seen. The spectrum analyzer

attenuation is also reduced, which lowers the noise floor.

Harmonic products at integer multiples of the fundamental

are thus revealed. This is the response using the AD9726 in

an uncalibrated state.

Figure 14 shows a response using the AD9726 in a calibrated

state. Harmonic distortion due to the nonlinearities of the

digital-to-analog conversion are virtually eliminated.

SYNC LOGIC OPERATION AND PROGRAMMING

Recall that a fixed setup and hold timing relationship between

the data clock input and the data bus must be established and

maintained. Recall also that the data bus and the DAC clock

must be frequency locked. Because of the sync logic, however,

the phase relationship between the data bus and the DAC clock

is internally optimized. Therefore, data arrival propagation

delays and concern about data transitions near the sampling

instant are eliminated.

Synchronization is automatically enabled upon reset. After data

arrives and synchronization is achieved, the sync logic contin-

uously monitors itself so that automatic adjustments are made if

phase drifts occur over time and/or temperature.

Note that the sync function and operation of the sync logic

block are transparent, automatic, and ongoing. No programming

is required. For applications where it is useful, however, the

following programmable control is provided.

SYNC Operating States

The sync logic can operate in one of three possible modes. The

default mode is fully automatic.

Fully automatic synchronization is accomplished by demulti-

plexing the incoming data stream into four channels, each

containing every fourth data-word. Data-words are present for

four DAC clock cycles. Data is remultiplexed by sampling each

channel with the optimum DAC clock cycle.

Initial synchronization is first established through a hardware

reset. This also fully enables the synchronization logic to mon-

itor and resynchronize, as necessary. The AD9726 resynchro-

nizes only if conditions change enough to alter the phase

between the data bus and the DAC clock by more than one full

clock cycle. In this event, an internal alarm occurs and is

followed by an automatic update. During resynchronization,

two data-words are typically lost or repeated.

In addition to fully automatic mode, two semi-automatic modes

are available.

Sync Manual Mode

In fully automatic mode, the AD9726 both detects when a

resynchronization is necessary and initiates an update. In

manual mode, automatic updating is disabled. Enable manual

mode by setting the SYNCMAN bit in SPI Register 0x02.

In manual mode, the sync logic still monitors incoming data

and the DAC clock, but it indicates the need for an update by

asserting the SYNCALRM bit (Bit 0 in Register 0x02). In this

mode, the user is expected to regularly poll the SYNCALRM

bit. When this bit is read back high, the user can issue a manual

sync update also by asserting the SYNCUPD bit (Bit 1) in SPI

SYNCALRM does not indicate that data is being lost but that

conditions are close to the point where data may be lost. The

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