R

F

R

G

V

OCM

INP

INM

CM

R

F

R

G

R

S

0.1mF

0.1mF

10mF

1mF

R

T

+3.3V

+5V

0.1mF

10mF

-

5V

THS4503

R

IN

R

IN

10 W

ADS5520

12-Bit / 125MSPS

POWER-SUPPLY SEQUENCE

AVDD

REFP

29

28

2 kW

1 W

1 mF

POWER-DOWN

REFERENCE CIRCUIT

ADS5520

Figure 42. Using the THS4503 with the ADS5520

ramps up within 10 ms. Optionally, it is recommended to put a 2-k

Ω resistor from REFP (pin 29) to AVDD as

shown in Figure 43. This helps to make the device more robust to power supply ramp-up timings.

Figure 43.

The device enters power-down in one of two ways: either by reducing the clock speed or by setting the PDN bit

through the serial programming interface. Using the reduced clock speed, power-down may be initiated for clock

frequency below 2 MSPS. The exact frequency at which the power down occurs varies from device to device.

Using the serial interface PDN bit to power down the device places the outputs in a high-impedance state and

only the internal reference remains on to reduce the power-up time. The power-down mode reduces power

dissipation to approximately 180 mW.

The ADS5520 has built-in internal reference generation, requiring no external circuitry on the printed circuit board

(PCB). For optimum performance, it is best to connect both REFP and REFM to ground with a 1-

µF decoupling

capacitor (the 1-

Ω resistor shown in Figure 44 is optional). In addition, an external 56.2-kΩ resistor should be

connected from IREF (pin 31) to AGND to set the proper current for the operation of the ADC, as shown in

Figure 44. No capacitor should be connected between pin 31 and ground; only the 56.2-k

Ω resistor should be

used.

Copyright © 2004–2008, Texas Instruments Incorporated

Submit Documentation Feedback

25

Product Folder Link(s): ADS5520