29

30

31

R EF P

R EF M

IR EF

1 W

1 W

56.2 kW

1 mF

1 mF

CLOCK INPUT

5 kW

5 kW

3 pF

3 pF

6 pF

CLKP

CLKM

CM

CM

ADS5520

Figure 44. REFP, REFM, and IREF Connections for Optimum Performance

The ADS5520 clock input can be driven with either a differential clock signal or a single-ended clock input, with

little or no difference in performance between both configurations. The common-mode voltage of the clock inputs

is set internally to CM (pin 17) using internal 5-k

Ω resistors that connect CLKP (pin 10) and CLKM (pin 11) to CM

(pin 17), as shown in Figure 45.

Figure 45. Clock Inputs

When driven with a single-ended CMOS clock input, it is best to connect CLKM (pin 11) to ground with a 0.01-

µF

capacitor, while CLKP is ac-coupled with a 0.01-

µF capacitor to the clock source, as shown in Figure 46.

26

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