APA600 datasheet(59/178 Pages) ACTEL

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ProASICPLUS Flash Family FPGAs

v5.9

2-49

Table 2-41 • Worst-Case Military Conditions

VDDP = 3.0V, VDD = 2.3V, TJ = 125°C for Military/MIL-STD-883

Macro Type

Description

Max. tINYH

Max. tINYL

Std.

GL33

3.3V, CMOS Input Levels3, No Pull-up Resistor

1.1

GL33S

3.3V, CMOS Input Levels3, No Pull-up Resistor, Schmitt Trigger

1.1

PECL

PPECL Input Levels

1.1

Notes:

1. tINYH = Input Pad-to-Y High

2. tINYL = Input Pad-to-Y Low

3. LVTTL delays are the same as CMOS delays.

4. For LP Macros, VDDP =2.3 V for delays.

Table 2-42 • Worst-Case Military Conditions

VDDP = 2.3V, VDD = 2.3V, TJ = 125°C for Military/MIL-STD-883

Macro Type

Description

Max. tINYH

Max. tINYL

Std.

GL25LP

2.5V, CMOS Input Levels3, Low Power

1.0

1.1

GL25LPS

2.5V, CMOS Input Levels3, Low Power, Schmitt Trigger

1.4

1.0

Notes:

1. tINYH = Input Pad-to-Y High

2. tINYL = Input Pad-to-Y Low

3. LVTTL delays are the same as CMOS delays.

4. For LP Macros, VDDP = 2.3 V for delays.

APA600 Datasheet(PDF) 59 Page - Actel Corporation

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