APA600 datasheet(64/178 Pages) ACTEL

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ProASICPLUS Flash Family FPGAs

2- 54

v5.9

Embedded Memory Specifications

This section discusses ProASICPLUS SRAM/FIFO embedded

memory and its interface signals, including timing

diagrams that show the relationships of signals as they

pertain to single embedded memory blocks (Table 2-51).

Table 2-13 on page 2-21 shows basic SRAM and FIFO

configurations. Simultaneous read and write to the same

location must be done with care. On such accesses the DI

bus is output to the DO bus. Refer to the ProASICPLUS

RAM and FIFO Blocks application note for more

information.

Enclosed Timing Diagrams—SRAM Mode:

•

"Synchronous SRAM Read, Access Timed Output

Strobe (Synchronous Transparent)" section on

page 2-55

•

"Synchronous SRAM Read, Pipeline Mode Outputs

(Synchronous Pipelined)" section on page 2-56

•

"Asynchronous SRAM Write" section on page 2-57

•

"Asynchronous SRAM Read, Address Controlled,

RDB=0" section on page 2-58

•

"Asynchronous SRAM Read, RDB Controlled"

section on page 2-58

•

"Synchronous SRAM Write"

•

Embedded Memory Specifications

The difference between synchronous transparent and

pipeline modes is the timing of all the output signals

from the memory. In transparent mode, the outputs will

change within the same clock cycle to reflect the data

requested by the currently valid access to the memory. If

clock cycles are short (high clock speed), the data

requires most of the clock cycle to change to valid values

(stable signals). Processing of this data in the same clock

cycle is nearly impossible. Most designers add registers at

all outputs of the memory to push the data processing

into the next clock cycle. An entire clock cycle can then

be used to process the data. To simplify use of this

memory

setup,

suitable

registers

have

been

implemented as part of the memory primitive and are

available to the user in the synchronous pipeline mode.

In this mode, the output signals will change shortly after

the second rising edge, following the initiation of the

read access.

Table 2-51 • Memory Block SRAM Interface Signals

SRAM Signal

Bits

In/Out

Description

WCLKS

Write clock used on synchronization on write side

RCLKS

Read clock used on synchronization on read side

RADDR[0:7]

Read address

RBLKB

True read block select (active Low)

RDB

True read pulse (active Low)

WADDR[0:7]

Write address

WBLKB

Write block select (active Low)

DI[0:8]

Input data bits [0:8], [8] can be used for parity In

WRB

Negative true write pulse

DO[0:8]

Out

Output data bits [0:8], [8] can be used for parity Out

RPE

Out

Read parity error (active High)

WPE

Out

Write parity error (active High)

PARODD

Selects odd parity generation/detect when high, even when low

Note: Not all signals shown are used in all modes.

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