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8902A Datasheet(PDF) 9 Page - Allegro MicroSystems

Part # 8902A
Description  3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER WITH BACK-EMF SENSING
PDF  12 Pages
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Manufacturer  ALLEGRO [Allegro MicroSystems]
Direct Link  http://www.allegromicro.com
Logo ALLEGRO - Allegro MicroSystems

8902A Datasheet(HTML) 9 Page - Allegro MicroSystems

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8902–A
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
Serial Port. The serial port functions to write various operational
and diagnostic modes to the A8902CLBA. The serial port DATA IN is
enabled/disabled by the CHIP SELECT terminal. When CHIP SE-
LECT is high the serial port is disabled and the chip is not affected by
changes in data at the DATA IN or CLOCK terminals.
To write data to the serial port, the CLOCK terminal should be low
prior to the CHIP SELECT terminal going low. Once CHIP SELECT
goes low, information on the DATA IN terminal is read into the shift
register on the positive-going transition of the CLOCK. There are 24
bits in the serial input port.
Data written into the serial port is latched and becomes active
upon the low-to-high transition of the CHIP SELECT terminal at the
end of the write cycle. D0 will be the last bit written to the serial port.
SERIAL PORT BIT DEFINITIONS
D0- Sleep/Run Mode; LOW = Sleep, HIGH = Run
This bit allows the device to be powered down when not in use.
D1- Step Mode; LOW = Normal Operation, HIGH = Step Only
When in the step-only mode the back-EMF commutation circuitry
is disabled and the power outputs are commutated by the start-
up oscillator. This mode is intended for device and system
testing.
D2- Brake; LOW = Run, HIGH = Brake.
D3 and D4 - These two bits set the output current limit:
D3
D4
Current Limit
0
0
1.2 A
0
1
1 A
1
0
600 mA
1
1
250 mA
D5 thru D18-This 14-bit word (active low) programs the REF time to set
desired motor speed.
Bit Number
Count Number
D5
16
D6
32
D7
64
D8
128
D9
256
D10
512
D11
1 024
D12
2 048
D13
4 096
D14
8 192
D15
16 384
D16
32 768
D17
65 536
D18
131 072
D19-Speed-control mode switch;
LOW = internal once-around speed signal,
HIGH = external sector data.
D20 and D21-These bits program the number
of motor poles for the once-around FCOM
counter:
D20
D21
Motor Poles
00
8
01
–
10
16
11
12
D22 and D23-Controls the multiplexer for
DATA OUT:
D22
D23
DATA OUT
0
0
TACH (once around or sector)
0
1
Thermal Shutdown
1
0
SYNC
1
1
FCOM
Reset. The RESET terminal when pulled
low clears all serial port bits, including the D0
latch, which puts the A8902CLBA in the sleep
mode.



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