Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

8902A Datasheet(PDF) 4 Page - Allegro MicroSystems

Part # 8902A
Description  3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER WITH BACK-EMF SENSING
PDF  12 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  ALLEGRO [Allegro MicroSystems]
Direct Link  http://www.allegromicro.com
Logo ALLEGRO - Allegro MicroSystems

8902A Datasheet(HTML) 4 Page - Allegro MicroSystems

  8902A Datasheet HTML 1Page - Allegro MicroSystems 8902A Datasheet HTML 2Page - Allegro MicroSystems 8902A Datasheet HTML 3Page - Allegro MicroSystems 8902A Datasheet HTML 4Page - Allegro MicroSystems 8902A Datasheet HTML 5Page - Allegro MicroSystems 8902A Datasheet HTML 6Page - Allegro MicroSystems 8902A Datasheet HTML 7Page - Allegro MicroSystems 8902A Datasheet HTML 8Page - Allegro MicroSystems 8902A Datasheet HTML 9Page - Allegro MicroSystems Next Button
Zoom Inzoom in Zoom Outzoom out
 4 / 12 page
background image
8902–A
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
SERIAL PORT TIMING CONDITIONS
Limits
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Units
CWD Current
ICWD
Charging
-9.0
-10
-11
µA
CWD Threshold Voltage
VTL
0.22
0.25
0.28
V
VTH
2.25
2.5
2.75
V
Max. FLL Oscillator Frequency
fOSC
VDD = 5.0 V, TA = 25
°C12
——
MHz
IOUT(MAX)
—
D3 = 0, D4 = 0
1.0
1.2
1.4
A
D3 = 0, D4 = 1
0.9
1.0
1.1
A
D3 = 1, D4 = 0
0.5
0.6
0.7
A
D3 = 1, D4 = 1
—
250
—
mA
BRAKE Threshold
VBRK
1.5
1.75
2.0
V
BRAKE Hysteresis Current
IBRKL
VBRK = 750 mV
—
20
—
µA
Transconductance Gain
gm
0.42
0.50
0.58
A/V
Centertap Resistors
RCT
5.0
10
13
k
Ω
Back-EMF Hysteresis
—
VBEMF - VCTAP at
5.0
20
37
mV
FCOM Transition
-5.0
-20
-37
mV
ELECTRICAL CHARACTERISTICS continued
DATA
CLOCK
Dwg. WP-019
A
C
B
D
C
D
CHIP SELECT
E
A. Minimum CHIP SELECT setup time before CLOCK rising edge .......... 100 ns
B. Minimum CHIP SELECT hold time after CLOCK rising edge ............... 150 ns
C. Minimum DATA setup time before CLOCK rising edge ........................ 150 ns
D. Minimum DATA hold time after CLOCK rising edge ............................. 150 ns
E. Minimum CLOCK low time before CHIP SELECT .................................. 50 ns
F. Maximum CLOCK frequency .............................................................. 3.3 MHz



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com