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MP8736 Datasheet(PDF) 14 Page - Monolithic Power Systems

Part # MP8736
Description  High Efficiency, Fast Transient, 6A, 19V Synchronous Buck Converter in a Tiny QFN20 (3x4mm) Package
PDF  23 Pages
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Manufacturer  MPS [Monolithic Power Systems]
Direct Link  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

MP8736 Datasheet(HTML) 14 Page - Monolithic Power Systems

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MP8736– HIGHEFFICIENCY,FAST TRANSIENT,6A, 19V SYNCHRONOUSBUCKCONVERTERIN ATINY3X4mmPACKAGE
MP8736 Rev. 1.34
www.MonolithicPower.com
14
4/18/2012
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
It turns into PWM mode once the output current
exceeds the critical level. After that, the switching
frequency stays fairly constant over the output
current range.
Switching Frequency
Constant on-time (COT) control is used in the
MP8736 and there is no dedicated oscillator in
the IC. The input voltage is feed-forwarded to the
on-time one-shot timer through the resistor R7.
The duty ratio is kept as VOUT/VIN. Hence, the
switching frequency is fairly constant over the
input voltage range.
The switching frequency
can be set as follows:
()
()
()
()
()
()
6
SW
IN
DEALY
IN
OUT
10
FkHz
6R7 k
V V
Tns
VV
0.4 V
V
=
×Ω
×+
−
(3)
Where TDELAY is the comparator delay. It’s about
40ns.
Jitter and FB Ramp Slope
Figure 4 and Figure 5 show jitter occurring in
both PWM mode and skip mode. When there is
noise in the VFB downward slope, the ON time of
HS-FET deviates from its intended location and
produces jitter. It is necessary to understand that
there is a relationship between a system’s
stability and the steepness of the VFB ripple’s
downward slope. The slope steepness of the VFB
ripple
dominates
in
noise
immunity.
The
magnitude of the VFB ripple doesn’t directly affect
the noise immunity directly.
Figure 4—Jitter in PWM Mode
Figure 5—Jitter in Skip Mode
Ramp with Large ESR Cap
In the case of POSCAP or other types of
capacitor with larger ESR is applied as output
capacitor. The ESR ripple dominates the output
ripple, and the slope on the FB is quite ESR
related. Figure 6 shows an equivalent circuit in
PWM mode with the HS-FET off and without an
external ramp circuit. Turn to application
information section for design steps with large
ESR caps.
R1
R2
ESR
POSCAP
SW
FB
Vo
L
Figure 6—Simplified Circuit in PWM Mode
without External Ramp Compensation
To realize the stability when no external ramp is
used, usually the ESR value should be chosen
as follow:
SW
ON
ESR
OUT
TT
0.7
2
R
C
+
×π
≥
(4)
Tsw is the switching period.
Ramp with small ESR Cap
When the output capacitors are ceramic ones,
the ESR ripple is not high enough to stabilize the
system, and external ramp compensation is
needed. Skip to application information section
for design steps with small ESR caps.



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