A40MX02 datasheet(84/142 Pages) MICROSEMI

84 / 142 page

40MX and 42MX FPGA Families

1- 80

R e v i sio n 1 1

Synchronous SRAM Operations (continued)

tADH

Address/Data Hold Time

0.0

tRENSU

Read Enable Set-Up

0.9

1.0

1.1

1.3

1.8

tRENH

Read Enable Hold

4.8

5.3

6.0

7.0

9.8

tWENSU

Write Enable Set-Up

3.8

4.2

4.8

5.6

7.8

tWENH

Write Enable Hold

0.0

tBENS

Block Enable Set-Up

3.9

4.3

4.9

5.7

8.0

tBENH

Block Enable Hold

0.0

Asynchronous SRAM Operations

tRPD

Asynchronous Access Time

11.3

12.6

14.3

16.8

23.5

tRDADV

Read Address Valid

12.3

13.7

15.5

18.2

25.5

tADSU

Address/Data Set-Up Time

2.3

2.5

2.8

3.4

4.8

tADH

Address/Data Hold Time

0.0

tRENSUA

Read Enable Set-Up to Address

Valid

0.9

1.0

1.1

1.3

1.8

tRENHA

Read Enable Hold

4.8

5.3

6.0

7.0

9.8

tWENSU

Write Enable Set-Up

3.8

4.2

4.8

5.6

7.8

tWENH

Write Enable Hold

0.0

tDOH

Data Out Hold Time

1.8

2.0

2.1

2.5

3.5

Input Module Propagation Delays

tINPY

Input Data Pad-to-Y

1.4

1.6

1.8

2.1

3.0

tINGO

Input Latch Gate-to-Output

2.0

2.2

2.5

2.9

4.1

tINH

Input Latch Hold

0.0

tINSU

Input Latch Set-Up

0.7

0.8

1.0

1.4

tILA

Latch Active Pulse Width

6.5

7.3

8.2

9.7

13.5

Table 1-39 • A42MX36 Timing Characteristics (Nominal 3.3 V Operation) (continued)

(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C)

–3 Speed

–2 Speed

–1 Speed

Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Notes:

1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for

estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules

can be obtained from the Timer utility.

4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.

External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an

external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.

5. Delays based on 35 pF loading.

A40MX02 Datasheet(PDF) 84 Page - Microsemi Corporation

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