A40MX02 datasheet(9/142 Pages) MICROSEMI

9 / 142 page

40MX and 42MX FPGA Families

Re vi s i on 11

1-5

uncommitted and can be assigned during routing. Each output segment spans four channels (two above

and two below), except near the top and bottom of the array, where edge effects occur. Long vertical

tracks contain either one or two segments. An example of vertical routing tracks and segments is shown

in Figure 1-6.

Antifuse Structures

An antifuse is a "normally open" structure. The use of antifuses to implement a programmable logic

device results in highly testable structures as well as efficient programming algorithms. There are no pre-

existing connections; temporary connections can be made using pass transistors. These temporary

connections can isolate individual antifuses to be programmed and individual circuit structures to be

tested, which can be done before and after programming. For instance, all metal tracks can be tested for

continuity and shorts between adjacent tracks, and the functionality of all logic modules can be verified.

Clock Networks

The 40MX devices have one global clock distribution network (CLK). A signal can be put on the CLK

network by being routed through the CLKBUF buffer.

In 42MX devices, there are two low-skew, high-fanout clock distribution networks, referred to as CLKA

and CLKB. Each network has a clock module (CLKMOD) that can select the source of the clock signal

from any of the following (Figure 1-7 on page 1-6):

•

Externally from the CLKA pad, using CLKBUF buffer

•

Externally from the CLKB pad, using CLKBUF buffer

•

Internally from the CLKINTA input, using CLKINT buffer

•

Internally from the CLKINTB input, using CLKINT buffer

The clock modules are located in the top row of I/O modules. Clock drivers and a dedicated horizontal

clock track are located in each horizontal routing channel.

Clock input pads in both 40MX and 42MX devices can also be used as normal I/Os, bypassing the clock

networks.

The A42MX36 device has four additional register control resources, called quadrant clock networks

(Figure 1-8 on page 1-6). Each quadrant clock provides a local, high-fanout resource to the contiguous

logic modules within its quadrant of the device. Quadrant clock signals can originate from specific I/O

Figure 1-6 •

MX Routing Structure

Segmented

Horizontal

Routing

Logic

Modules

Antifuses

Vertical Routing Tracks

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