ZSSC3036

Low-Power 16-Bit Sensor Signal Conditioner IC

Data Sheet

May 28, 2013

© 2013 Zentrum Mikroelektronik Dresden AG

— Rev. 1.20

All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without

the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.

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MSB

SCLK (CPOL=0)

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

LSB

MSB

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

LSB

SCLK (CPOL=1)

MOSI

MISO

/SS

SAMPLE

CPHA=0

Table 3.6

Mode Status

Status[4:3]

Mode

00

Normal Mode

01

Command Mode

10

ZMDI-Reserved

11

Command Mode and Reserved

Further status information is provided by the EOC pin. The EOC pin is set high when a measurement and

calculation have been completed.

3.5.2.

SPI

The SPI Mode is available when the SEL pin = 0. The polarity and phase of the SPI clock are programmable via

selects which edge of SCLK latches data, and CPOL (bit 11), which indicates whether SCLK is high or low when it

is idle. The polarity of the SS signal and pin are programmable via the SS_polarity setting (bit 9). The different

combinations of polarity and phase are illustrated in the figures below.

Figure 3.3

SPI Configuration CPHA=0