AM79C873 datasheet(8/44 Pages) AMD

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Am79C873

PRELIMINARY

PIN DESCRIPTIONS

MII Interface

TX_ER/TXD4

Transmit Error

Input

In 100 Mbps mode, if this signal is asserted high and

TX_EN is active, the HALT symbol is substituted for the

actual data nibble. In 10 Mbps mode, this input

is ignored.

In bypass modes (BP4B5B or BPALIGN), TX_ER be-

comes the TXD4 pin, the ﬁfth TXD data bit.

TXD[3:0]

Transmit Data

Input

These are the transmit data input pins for nibble

data from the MII in 100 Mbps or 10 Mbps nibble

mode (25 MHz for 100 Mbps mode, 2.5 MHz for 10

Mbps nibble mode).

In 10 Mbps serial mode, the TXD0 pin is used as the

serial data input pin. TXD[3:1] are ignored.

TX_EN

Transmit Enable

Input

Active high input indicates the presence of valid nib-

ble data on TXD[3:0] for both 100 Mbps or 10 Mbps

nibble mode.

In 10 Mbps serial mode, active high indicates the pres-

ence of valid 10 Mbps data on TXD0.

TX_CLK

Transmit Clock

Output/Z1

This pin provides the transmit clock output from the

NetPHY-1 deviceas follows:

- 25 MHz nibble transmit clock derived from trans-

mit Phase Locked Loop (TX PLL) in 100BASE-TX

mode

- 2.5 MHz transmit clock in 10BASE-T nibble mode

- 10 MHz transmit clock in 10BASE-T serial mode

MDC

Management Data Clock

Input

This pin is the synchronous clock to the MDIO manage-

ment data input/output serial interface which is asyn-

chronous to transmit and receive clocks. The maximum

clock rate is 2.5 MHz.

MDIO

Management Data I/O

Input/Output

This pin is the bidirectional management instruction/

data signal that may be driven by the station manage-

ment entity or the PHY. This pin requires a 1.5 K

Ω pull-

up resistor.

RXD[3:0]

Receive Data

Output/Z1

Nibble wide receive data (synchronous to RX_CLK - 25

MHz for 100BASE-TX mode, 2.5 MHz for 10BASE-T

nibble mode). Data is driven on the falling edge of

RX_CLK.

In 10 Mbps serial mode, the RXD0 pin is used as the

data output pin. RXD[3:1] are ignored.

RX_CLK

Receive Clock

Output/Z1

Provides the recovered receive clock for different

modes of operation:

- 25 MHz nibble clock in 100 Mbps mode

- 2.5 MHz nibble clock in 10 Mbps nibble mode

- 10 MHz receive clock in 10 Mbps serial mode

CRS

Carrier Sense

Output/Z1

This pin is asserted high to indicate the presence of

carrier due to receive or transmit activities in 10BASE-

T or 100BASE-TX Half Duplex modes.

In Repeater, when Full Duplex or Loopback mode is a

logic 1, it indicates the presence of carrier due only to

receive activity.

COL

Collision Detect

Output/Z1

This pin is asserted high to indicate detection of colli-

sion conditions in 10 Mbps and 100 Mbps Half Duplex-

modes. In 10BASE-T Half Duplex mode with Heartbeat

set active (bit 13, register 18h), it is also asserted for a

duration of approximately 1ms at the end of transmis-

sion to indicate heartbeat. In Full Duplex mode, this

signal is always logic 0. There is no heartbeat function

in Full Duplex mode.

RX_DV

Receive Data Valid

Output/Z1

This pin is asserted high to indicate that valid data is

present on RXD[3:0].

RX_ER/RXD4

Receive Error

Output/Z1

This pin is asserted high to indicate that an invalid sym-

bol has been detected inside a received packet in 100

Mbps mode.

In a bypass mode (BP4B5B or BPALIGN modes),

RX_ER becomes RXD4, the ﬁfth RXD data bit of the

5B symbols.

1. Goes to high impedance.

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