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AM79C983A Datasheet(PDF) 9 Page - Advanced Micro Devices

Part # AM79C983A
Description  Integrated Multiport Repeater 2 (IMR2??
PDF  60 Pages
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Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM79C983A Datasheet(HTML) 9 Page - Advanced Micro Devices

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Am79C983A
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PRELIMINARY
Microprocessor Interface .............................................................................................................. 29
Management Functions .......................................................................................................... 29
Status Register ................................................................................................................ 30
Register Bank 0: Repeater Registers .............................................................................. 30
Source Address Match Register .............................................................................. 30
Total Octets.............................................................................................................. 31
Transmit Collisions ................................................................................................... 31
Configuration Register ............................................................................................. 31
Repeater Status ....................................................................................................... 31
QuIET Device Transceiver ID Register .................................................................... 31
Repeater Device and Revision Register .................................................................. 32
Device Configuration................................................................................................ 32
Register Bank 1: Interrupts .............................................................................................. 32
Port Partition Status Change Interrupt ..................................................................... 32
Runts with Good FCS Interrupt ................................................................................ 32
Link Status Change Interrupt ................................................................................... 32
Loopback Error Change Interrupt............................................................................. 33
Polarity Change Interrupt ......................................................................................... 33
SQE Test Error Change Interrupt............................................................................. 33
Source Address Changed Interrupt.......................................................................... 33
Intruder Interrupt ...................................................................................................... 33
Source Address Match Interrupt .............................................................................. 33
Data Rate Mismatch Interrupt .................................................................................. 34
Transceiver Interface Status .................................................................................... 34
Transceiver Interface Change Interrupt ................................................................... 34
Jabber Interrupt........................................................................................................ 34
Register Bank 2: Interrupt Control Registers ................................................................... 34
Partition Status Change Interrupt Enable................................................................. 34
Runts with Good FCS Interrupt Enable.................................................................... 34
Link Status Change Interrupt Enable ....................................................................... 35
Loopback Error Change Interrupt Enable ................................................................ 35
Polarity Change Interrupt Enable ............................................................................. 35
SQE Test Error Change Interrupt Enable ................................................................ 35
Source Address Changed Interrupt Enable ............................................................. 35
Intruder Interrupt Enable .......................................................................................... 35
Multicast Address Pass Enable................................................................................ 36
Data Rate Mismatch Interrupt Enable ...................................................................... 36
Last Source Address Compare Enable.................................................................... 36
Preferred Address Compare Enable ........................................................................ 36
Transceiver Interface Changed Interrupt Enable ..................................................... 36
Jabber Interrupt Enable............................................................................................ 36
Register Bank 3: Port Control Registers .......................................................................... 37
Alternative Reconnection Algorithm Enable............................................................. 37
Link Test Enable ...................................................................................................... 37
Link Pulse Transmit Enable ..................................................................................... 37
Automatic Receiver Polarity Reversal Enable.......................................................... 37
SQE Mask Enable.................................................................................................... 37
Port Enable/Disable ................................................................................................. 37
Port Switching Control.............................................................................................. 37
Extended Distance Enable....................................................................................... 38
Automatic Last Source Address Intrusion Control ................................................... 38
Automatic Preferred Source Address Intrusion Control ........................................... 38
Last Source Address Lock Control........................................................................... 38
Register Bank 4: Port Status Registers ........................................................................... 39
Partitioning Status of Ports....................................................................................... 39
Link Test Status of Ports .......................................................................................... 39
Loopback Error Status ............................................................................................. 39
Receive Polarity Status ............................................................................................ 39



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