W25X05CLZPIG datasheet(15/51 Pages) WINBOND

15 / 51 page

W25X05CL/10CL/20CL

Publication Release Date: March 23, 2012

- 15 -

Revision B

8.2.3 Write Enable (06h)

The Write Enable instruction (Figure 4) sets the Write Enable Latch (WEL) bit in the Status Register to

a 1. The WEL bit must be set prior to every Page Program, Sector Erase, Block Erase, Chip Erase

and Write Status Register instruction. The Write Enable instruction is entered by driving /CS low,

shifting the instruction code “06h” into the Data Input (DI) pin on the rising edge of CLK, and then

driving /CS high.

Figure 4. Write Enable Instruction Sequence Diagram

8.2.4 Write Enable for Volatile Status Register (50h)

The non-volatile Status Register bits described in section 8.1 can also be written to as volatile bits.

This gives more flexibility to change the system configuration and memory protection schemes quickly

without waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status

Volatile Status Register (50h) instruction must be issued prior to a Write Status Register (01h)

instruction. Write Enable for Volatile Status Register instruction (Figure 5) will not set the Write Enable

Latch (WEL) bit, it is only valid for the Write Status Register instruction to change the volatile Status

Figure 5. Write Enable for Volatile Status Register Instruction Sequence Diagram

/CS

CLK

(IO

Mode 0

Mode 3

Mode 0

Mode 3

Instruction (06h)

High Impedance

Instruction (50h)

W25X05CLZPIG Datasheet(PDF) 15 Page - Winbond