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STM32F207IC Datasheet(PDF) 94 Page - STMicroelectronics |
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STM32F207IC Datasheet(HTML) 94 Page - STMicroelectronics |
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94 / 163 page  Electrical characteristics STM32F205xx, STM32F207xx 94/163 Doc ID 15818 Rev 7 5.3.17 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 41). Unless otherwise specified, the parameters given in Table 44 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 10. Figure 37. Recommended NRST pin protection 2. The reset network protects the device against parasitic resets. 3. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 44. Otherwise the reset is not taken into account by the device. Table 44. NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit VIL(NRST) (1) 1. Guaranteed by design, not tested in production. NRST Input low level voltage –0.5 - 0.8 V VIH(NRST) (1) NRST Input high level voltage 2 - VDD+0.5 Vhys(NRST) NRST Schmitt trigger voltage hysteresis - 200 - mV RPU Weak pull-up equivalent resistor(2) 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order) . VIN = VSS 30 40 50 k Ω VF(NRST) (1) NRST Input filtered pulse - - 100 ns VNF(NRST) (1) NRST Input not filtered pulse VDD > 2.7 V 300 - - ns TNRST_OUT Generated reset pulse duration Internal Reset source 20 - - µs |
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