IO96PDB2V1 datasheet(44/242 Pages) MICROSEMI

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ProASIC3L DC and Switching Characteristics

2-28

Revision 13

Table 2-30 • Summary of I/O Timing Characteristics—Software Default Settings

–1 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst

Case VCCI

Advanced I/O Banks

I/O Standard

3.3 V LVTTL /

3.3 V LVCMOS

12 mA 12 mA High

– 0.46 1.83 0.03 0.78 0.33 1.87 1.39 2.46 2.74 3.58 3.10 ns

3.3 V LVCMOS

Wide Range1,2

100 µA 12 mA High

–

2.5 V LVCMOS

12 mA 12 mA High

– 0.46 1.85 0.03 1.00 0.33 1.88 1.55 2.53 2.63 3.59 3.26 ns

1.8 V LVCMOS 12 mA 12 mA High

– 0.46 2.04 0.03 0.93 0.33 2.08 1.73 2.83 3.12 3.79 3.45 ns

1.5 V LVCMOS 12 mA 12 mA High

– 0.46 2.33 0.03 1.10 0.33 2.37 2.01 3.02 3.22 4.08 3.72 ns

3.3 V PCI

Per

PCI

spec.

–

High

25 3 0.46 2.05 0.03 0.66 0.33 2.09 1.49 2.46 2.74 3.80 3.21 ns

3.3 V PCI-X

Per

PCI-X

spec.

–

High 10

253 0.46 2.05 0.03 0.64 0.33 2.09 1.49 2.46 2.74 3.80 3.21 ns

LVDS

24 mA

–

High

–

– 0.46 1.40 0.03 1.23 N/A N/A N/A N/A N/A N/A N/A ns

LVPECL

24 mA

–

High

–

– 0.46 1.38 0.03 1.08 N/A N/A N/A N/A N/A N/A N/A ns

Notes:

1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is

±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the

IBIS models.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

3. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-81 for

connectivity. This resistor is not required during normal operation.

4. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

IO96PDB2V1 Datasheet(PDF) 44 Page - Microsemi Corporation

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