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IO96PDB2V1 Datasheet(PDF) 10 Page - Microsemi Corporation |
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IO96PDB2V1 Datasheet(HTML) 10 Page - Microsemi Corporation |
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10 / 242 page  ProASIC3L Device Family Overview 1-4 Revision 13 Figure 1-1 • ProASIC3L Device Architecture Overview with Four I/O Banks (A3P250L, A3P600L, and A3P1000L) Figure 1-2 • ProASIC3EL Device Architecture Overview ISP AES Decryption* User Nonvolatile FlashRom Flash*Freeze Technology Charge Pumps RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block (A3P600L and A3P1000L) RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block VersaTile CCC I/Os Bank 0 Bank 2 4,608-Bit Dual-Port SRAM or FIFO Block VersaTile RAM Block CCC Pro I/Os 4,608-Bit Dual-Port SRAM or FIFO Block RAM Block ISP AES Decryption* User Nonvolatile FlashRom Flash*Freeze Technology Charge Pumps |
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