R5F564MFDDBG datasheet(10/67 Pages) RENESAS

10 / 67 page

RX64M Group

1. Overview

Under development Preliminary document

Specifications in this document are tentative and subject to change.

R01DS0173EJ0090 Rev.0.90

Page 10 of 67

Feb 28, 2014

Note 1. Magic PacketTM is a registered trademark of Advanced Micro Devices, Inc.

Note 2. Setting is only possible when the input sampling rate 44.1 kHz is selected.

Note 3. Optional

Encryption

function

AES*3

 Key lengths: 128, 196, and 256 bits

 Support for CFB, OFB, and CMAC operating modes

 Speed of calculations: 128-bit key length in 22 cycles

192-bit key length in 26 cycles

256-bit key length in 30 cycles

 Compliant with FIPS PUB 197

DES*3

 Key lengths: 56 bits (DES)/3 × 56 bits (T-DES)

 Support for DES and triple DES

 Support for ECB and CBC operating modes

 Speed of calculations: 6 clock cycles in single DES mode

14 clock cycles in triple DES mode

 Compliant with FIPS PUB 46-3

 Compliant with FIPS PUB 81

SHA*3

 Support for SHA-1 (128), SHA-2 (224 or 256), and HMAC (160, 224, or 256)

 Speed of calculations: 50 clock cycles in SHA-1 mode

42 clock cycles in SHA-224 mode

42 clock cycles in SHA-256 mode

 Compliant with SHA as defined in FIPS PUB 180-1 and -2

 Compliant with HMAC as defined in FIPS PUB 198

True random number

generator (RNG)*3

 Length of random numbers: 16 bits

 Generation of random-number-generated interrupts after a number is generated

 Random number generation time: 2.8 ms (typ)

Operating frequency

Up to 120 MHz

Power supply voltage

VCC = AVCC0 = AVCC1 = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 to AVCC0,

VCC_USBA = AVCC_USBA = 2.7 to 3.6 V,

VBATT = 2.0 to 3.6 V

Operating temperature

D-version:

40 to +85°C

G-version:

40 to +TBD

Package

177-pin TFLGA (PTLG0177KA-A) (in planning)

176-pin LFBGA (PLBG0176GA-A) (in planning)

176-pin LQFP (PLQP0176KB-A)

145-pin TFLGA (PTLG0145KA-A) (in planning)

144-pin LQFP (PLQP0144KA-A)

100-pin TFLGA (PTLG0100JA-A) (in planning)

100-pin LQFP (PLQP0100KB-A)

On-chip debugging system

 E1 emulator (JTAG and FINE interfaces)

 E20 emulator (JTAG interface)

Table 1.1

Outline of Specifications (9/9)

Classification

Module/Function

Description

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