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THS4281DRG4 Datasheet(PDF) 2 Page - National Semiconductor (TI) |
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THS4281DRG4 Datasheet(HTML) 2 Page - National Semiconductor (TI) |
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2 / 37 page ![]() THS4281 SLOS432A – APRIL 2004 – REVISED NOVEMBER 2009 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range (unless otherwise noted). UNIT Supply voltage, VS– to VS+ 16.5 V Input voltage, VI ±VS ± 0.5 V Differential input voltage, VID ±2 V Output current, IO ±100 mA Continuous power dissipation See Dissipation Ratings Table Maximum junction temperature, any condition, (2) TJ +150°C Maximum junction temperature, continuous operation, long-term reliability(2) TJ +125°C Storage temperature range, Tstg –65°C to +150°C HBM 3500 V ESD ratings CDM 1500 V MM 100 V (1) The absolute maximum ratings under any condition is limited by the constraints of the silicon process. Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. (2) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may result in reduced reliability and/or lifetime of the device. recommended operating conditions. RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT Dual supply ±1.35 ±8.25 Supply voltage, (VS+ and VS –) V Single supply 2.7 16.5 DISSIPATION RATINGS TABLE PER PACKAGE θJA (1) POWER RATING(2) θJC PACKAGE (°C/W) (°C/W) TA < +25°C TA = +85°C DBV (5) 55 255.4 391 mW 156 mW D (8) 38.3 97.5 1.02 W 410 mW DGK (8) 71.5 180.8 553 mW 221 mW (1) This data was taken using the JEDEC standard High-K test PCB. (2) Power rating is determined with a junction temperature of +125°C. This is the point where distortion starts to substantially increase. Thermal management of the final PCB should strive to keep the junction temperature at or below +125°C for best performance and long term reliability. 2 Submit Documentation Feedback Copyright © 2004–2009, Texas Instruments Incorporated Product Folder Link(s): THS4281 |
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