CS4218 datasheet(18/44 Pages) CIRRUS

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Master Sub-Mode (SM3-M)

Master su b- mod e is selected by sett in g

MF4:MA = 1, which configures SSYNC and

SCLK as outputs from the CS4218. During

power down, SSYNC and SCLK are driven high

impedance, and during reset they both are driven

low. In Master sub-mode the number of bits per

frame determines how many codecs can occupy

the serial bus and is illustrated in Figure 14.

Bits Per Frame (Master Sub-Modes)

MF8:SFS2 selects the number of bits per frame.

The two options are MF8:SFS2 = 1 which se-

lects 128 bits per frame, and MF8:SFS2 = 0

which selects 64 bits per frame.

Selecting 128 bits per frame (MF8:SFS2 = 1) al-

lows two CS4218s to operate from the same

serial bus since each codec requires 64 bit peri-

ods. The sub-frame used by an individual codec

is selected using MF7:SFS1. MF7:SFS1 = 0 se-

lects sub-frame 1 which is the first 64 bits

following the SSYNC pulse. MF7:SFS1 = 1 se-

lects sub-frame 2 which is the last 64 bits of the

frame.

Selecting 64 bits per frame (MF8:SFS2 = 0) al-

lows only one CS4218 to occupy the serial port.

Since there is only one sub-frame (which is

equal to one frame), MF7:SFS1 is defined differ-

ently in this mode. MF7:SFS1 selects the format

of SSYNC. MF7:SFS1 = 0 selects an SSYNC

pulse one SCLK period high, directly preceding

the data as shown in the center portion of Fig-

ure 14. This format is used for all other master

and slave sub-modes in SM3. If MF7:SFS1 = 1,

an alternate SSYNC format is chosen in which

SSYNC is high during the entire Word A

(32 bits), which includes the left sample, and

low for the entire Word B (32 bits), which in-

cludes the right sample. This alternate format for

SSYNC is illustrated in the bottom portion of

Figure 14 and is only available in SM3-M and

SM3-MM sub-modes with 64 bits per frame. A

more detailed timing diagram for the 64 bits-per-

frame master sub-modes is shown in Figure 15.

Sample Frequency Selection (Master

Sub-Modes)

In SM3-M and SM3-MM sub-modes, the multi-

function pins MF1:F1, MF2:F2, and MF3:F3 are

used to select the sample frequency divider. Ta-

ble 3 lists the decoding for the sample frequency

select pins where the sample frequency selected

is CLKIN/N. Also shown are the sample fre-

quencies obtained by using one of two example

ma ster clo ck s : either 12.288 MHz or

11.2896 MHz. Changing sample frequency auto-

matically initiates a calibration cycle.

Fs (kHz)

MF1:

MF2:

MF3:

with CLKIN

or 16xCLKIN

12.288

11.2896

MHz

256

48.00

44.10

384

32.00

29.40

512

24.00

22.05

640

19.20

17.64

768

16.00

14.70

1024

12.00

11.025

1280

9.60

8.82

1536

8.00

7.35

Table 3. SM3-M/SM3-MM/SM5, Fs Select

CS4218

DS135F1

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