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CS5126 Datasheet(PDF) 23 Page - Cirrus Logic |
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CS5126 Datasheet(HTML) 23 Page - Cirrus Logic |
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23 / 32 page ![]() 4.99 k In A In B 4.99 k 1 nF C0G ceramic 4.99 k 4.99 k 1 nF C0G ceramic V+ V- 50 k 1 M 121 k Offset ADJ 1 M 1 nF C0G ceramic 6.81 k V+ V- 1 nF C0G ceramic 200 Vout +15 V -15 V 10 V+ V- 1 µF tantalum 35 V 10 1 µF tantalum 35 V 0.01 µF ceramic 0.01 µF ceramic OP27 2 3 7 4 6 Notes: 1) In B and offset adjust are optional. 2) Offset adjustment range is + 10 mV with values shown. Figure 2. Example Input Buffer Circuit (not provided on the CDB5126 evaluation board) OP27 C6 0.1 µF C7 0.01 µF 2 3 4 7 6 R3 22 R4 47 k R5 1 k +15V -15V C4 0.1 µF C8 16 µF + C9 0.1 µF TP4 J2 VREF AGND C1 10 µF + C2 0.1 µF R2 1 k R1 25 k OUT TRIM GND IN LT1019-5 U2 +15V 2 4 5 6 CW 20 22 TP1 U1 CS5126 Figure 3. Voltage Reference CDB5126 DS32DB5 23 |
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