P1

0 - Select external clock via BNC connector

P2

1 - Select external HOLD via BNC connector.

P3

∗

Connect SCLK to on-board shift registers.

P4

1 - Drive L/R select at 48 kHz from the on-board timing generator.

2 - Pull L/R select pin low, selecting the right channel only.

P6

∗

Connect the OE pins of the shift registers to ground. Permanently enables the 3-state output buffers.

P7

1 - Connects the NAND gate outputs (U11, pin 11) to the shift registers.

P8

2 - Connects TRKL and TRKR

ANDED together to P5. This signal can be used as an "End of Convert"

indicator.

3 - Connects TRKL to P5.

4 - Connects TRKR to P5.

P9

∗

Connects the on-board generated SCLK to the rest of the on-board circuitry.

P10

1 - Causes the on-board Data Ready generating circuit to flag data ready every left conversion. P4 must

be in position 1 for this to work.

2 - Causes the on-board Data Ready generating circuit to flag data ready every right conversion. P4 must

be in position 1 for this to work.

P11

0 - Connects TRKL & TRKR to U10B, the handshake flip-flop.

P12

1 - Connects the TRKL & TRKR to U11, pin 13.

∗

Factory default state for CS5126

Table 1. Solder Link Options

Table 2. Shorting Plug Selectable Options

J1

-

Joins analog ground to digital ground on the board.

J2

-

Joins LT1019-5 reference directly to the VREF pin on the ADC. Before doing this, break the connection

between R3 and the ADC VREF pin by using a twist drill to remove the central feedthrough. This option

allows evaluation of different reference configurations.

J4

-

Connects an external clock to CLKIN on the ADC.

CDB5126

DS32DB5

27