CY7C0430V
PRELIMINARY
24
Counter-Mask Register
The burst counter has a mask register that controls when and
where the counter wraps. An interrupt flag (CNTINT) is assert-
ed for one clock cycle when the unmasked portion of the
counter address wraps around from all ones (CNTINC must be
asserted) to all zeros. The example in Figure 2 shows the
counter mask register loaded with a mask value of 003F un-
masking the first 6 bits with bit “0” as the LSB and bit “15” as
the MSB. The maximum value the mask register can be loaded
with is FFFF. Setting the mask register to this value allows the
counter to access the entire memory space. The address
counter is then loaded with an initial value of XXX8. The
“blocked” addresses (in this case, the 6th address through the
15th address) are loaded with an address but do not increment
once loaded. The counter address will start at address XXX8.
With CNTINC asserted LOW, the counter will increment its
internal address value till it reaches the mask register value of
3F and wraps around the memory block to location XXX0.
Therefore, the counter uses the mask-register to define
wrap-around point. The mask register of every port is loaded
when MKLD (mask register load) for that port is LOW. When
MKRD is LOW, the value of the mask register can be read out
on address lines in a manner similar to counter read back op-
eration (see Table 2 for required conditions).
When the burst counter is loaded with an address higher than
the mask register value, the higher addresses will form the
masked portion of the counter address and are called blocked
addresses. The blocked addresses will not be changed or af-
fected by the counter increment operation. The only exception
is mask register bit 0. It can be masked to allow the address
counter to increment by two. If the mask register bit 0 is loaded
with a logic value of “0,” then address counter bit 0 is masked
and can not be changed during counter increment operation.
If the loaded value for address counter bit 0 is “0,” the counter
will increment by two and the address values are even. If the
loaded value for address counter bit 0 is “1,” the counter will
increment by two and the address values are odd. This oper-
ations allows the user to achieve a 36-bit interface using any
two ports, where the counter of one port counts even address-
es and the counter of the other port counts odd addresses.
This even-odd address scheme stores one half of the 36-bit
word in even memory locations, and the other half in odd mem-
ory locations. CNTINT will be asserted when the unmasked
portion of the counter wraps to all zeros. Loading mask regis-
ter bit 0 with “1” allows the counter to increment the address
value sequentially.
Table 2 groups the operations of the mask register with the
operations of the address counter. Address counter and mask
register signals are all synchronized to the port's clock CLK.
Master reset (MRST) is the only asynchronous signal listed on
Table 2. Signals are listed based on their priority going from
left column to right column with MRST being the highest. A
LOW on MRST will reset both counter register to all zeros and
mask register to all ones. On the other hand, a LOW on
CNTRST will only clear the address counter register to zeros
and the mask register will remain intact.
There are four operations for the counter and mask register:
1. Load operation: When CNTLD or MKLD is LOW, the ad-
dress counter or the mask register is loaded with the ad-
dress value presented at the address lines. This value rang-
es from 0 to FFFF (64K). The mask register load operation
has a higher priority over the address counter load opera-
tion.
2. Increment: Once the address counter is loaded with an ex-
ternal address, the counter can internally increment the ad-
dress value by asserting CNTINC LOW. The counter can
215 214
26
21
25
22
24 23
20
215 214
26
21
25
22
24 23
20
215 214
26
21
25
22
24 23
20
215 214
26
21
25
22
24 23
20
H
H
H
L
11
0’s
1
0
1
0
1
01
00
X’s
1
X
0
X
0
X0
11
X’s
1
X
1
X
1
X1
00
X’s
0
X
0
X
0
X0
Blocked Address
Counter Address
Mask
Register
bit-0
Address
Counter
bit-0
CNTINT
Example:
Load
Counter-Mask
Register = 3F
Load
Address
Counter = 8
Max
Address
Register
Max + 1
Address
Register
Figure 2. Programmable Counter-Mask Register Operation[46]
Note:
46. The “X” in this diagram represents the counter upper-bits.
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