DS2181A

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DESCRIPTION

The DS2181A is designed for use in CEPT networks and supports all logical requirements of CCITT Red

Book Recommendations G.704, G.706 and G.732. The transmit side generates framing patterns and

CRC4 codes, formats outgoing channel and signaling data, and produces network alarm codes when

enabled. The receive side decodes the incoming data and establishes frame, CAS multiframe, and CRC4

multiframe alignments. Once synchronized, the device extracts channel, signaling, and alarm data.

A serial port allows access to 14 on-chip control and status registers in the processor mode. In this mode,

a host processor controls features such as error logging, per-channel code manipulation, and alteration of

the receive synchronizer algorithm.

The hardware mode is intended for preliminary system prototyping and/or retrofitting into existing

systems. This mode requires no host processor and disables special features available in the processor

mode.

DS2180A BLOCK DIAGRAM Figure 1