EP1C3 datasheet(3/385 Pages) ETC2

3 / 385 page

Altera Corporation

iii

Preliminary

Contents

Chapter Revision Dates ........................................................................... xi

About this Handbook ............................................................................. xiii

How to Find Information ..................................................................................................................... xiii

How to Contact Altera .......................................................................................................................... xiii

Typographic Conventions .................................................................................................................... xiv

Section I. Cyclone FPGA Family Data Sheet

Revision History .................................................................................................................................... 2–1

Chapter 1. Introduction

Introduction ............................................................................................................................................ 1–1

Features ................................................................................................................................................... 1–1

Document Revision History ................................................................................................................. 1–3

Chapter 2. Cyclone Architecture

Functional Description .......................................................................................................................... 2–1

Logic Array Blocks ................................................................................................................................ 2–3

LAB Interconnects ............................................................................................................................ 2–3

LAB Control Signals ......................................................................................................................... 2–4

Logic Elements ....................................................................................................................................... 2–5

LUT Chain and Register Chain ...................................................................................................... 2–7

addnsub Signal ................................................................................................................................. 2–7

LE Operating Modes ........................................................................................................................ 2–7

MultiTrack Interconnect ..................................................................................................................... 2–12

Embedded Memory ............................................................................................................................. 2–18

Memory Modes ............................................................................................................................... 2–18

Parity Bit Support ........................................................................................................................... 2–20

Shift Register Support .................................................................................................................... 2–20

Memory Configuration Sizes ........................................................................................................ 2–21

Byte Enables .................................................................................................................................... 2–23

Control Signals and M4K Interface .............................................................................................. 2–23

Independent Clock Mode .............................................................................................................. 2–25

Input/Output Clock Mode ........................................................................................................... 2–25

Read/Write Clock Mode ............................................................................................................... 2–28

Single-Port Mode ............................................................................................................................ 2–29

Global Clock Network and Phase-Locked Loops ........................................................................... 2–29

Global Clock Network ................................................................................................................... 2–29

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