EP1C3 datasheet(49/385 Pages) ETC2

49 / 385 page

Altera Corporation

2–29

May 2008

Preliminary

Global Clock Network and Phase-Locked Loops

Single-Port Mode

The M4K memory blocks also support single-port mode, used when

simultaneous reads and writes are not required. See Figure 2–21. A single

M4K memory block can support up to two single-port mode RAM blocks

if each RAM block is less than or equal to 2K bits in size.

Figure 2–21. Single-Port Mode

Note (1)

Note to Figure 2–21:

(1)

Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both

read and write operations.

Global Clock

Network and

Phase-Locked

Loops

Cyclone devices provide a global clock network and up to two PLLs for a

complete clock management solution.

Global Clock Network

There are four dedicated clock pins (

CLK[3..0], two pins on the left side

and two pins on the right side) that drive the global clock network, as

shown in Figure 2–22. PLL outputs, logic array, and dual-purpose clock

(

DPCLK[7..0]) pins can also drive the global clock network.

ENA

data[ ]

address[ ]

RAM/ROM

256

× 16

512

× 8

1,024

× 4

2,048

× 2

4,096

× 1

Data In

Address

Write Enable

Data Out

outclken

inclken

inclock

outclock

Write

Pulse

Generator

wren

6 LAB Row

Clocks

To MultiTrack

Interconnect

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