EM78P458AP datasheet(33/76 Pages) EMC

33 / 76 page

EM78P458/459

OTP ROM

1 = The Vref of the ADC is connected to P53/VREF.

• CE (Bit 6): Control bit used to enable comparator.

0 = Disable comparator

1 = Enable comparator

• COE (Bit 5): Set P57 as the output of the comparator

0 = the comparator acts as an OP if CE=1.

1 = act as a comparator if CE=1.

• IMS2~IMS0 (Bit 4 ~ Bit 2): ADC configuration definition bit.

• CKR1 and CKR0 (Bit 1 and Bit 0): The conversion time select.

00 = Fosc/4;

01 = Fosc/16;

10 = Fsco/64;

11 = The oscillator clock source of ADC is from WDT ring oscillator frequency.

( frequency=256/18ms≒14.2Khz)

1.3 GCON/IOC90

As shown in Fig. 12, OP1 and OP2, the gain amplifiers, are located in the middle of the analog

input pins (ADC1 and ADC5) and the 8-1analog switch. The GCON register controls the gains.

Table 7 Table 7 Shows the Gains and the Operating Range of ADC.

BIT

SYMBOL

OP2E

OP1E

G22

G21

G20

G12

G11

G10

*Init_Value

Table 8 The Gains and the Operating Range of ADC

G10:G12/G20:G22

Gain

Range of Operating Voltage

000

0 ~ Vref

001

0 ~ (1/2)Vref

010

0 ~ (1/4)Vref

011

0 ~ (1/8)Vref

100

0 ~ (1/16)Vref

101

0 ~ (1/32)Vref

<Note> Vref can not be less than 3 volts.

2. ADC Data Register (ADDATA/RA)

When the A/D conversion is complete, the result is loaded to the ADDATA. The START/END bit is

clear, and the ADIF is set.

This specification is subject to change without prior notice.

06.25.2004 (V1.4)

EM78P458AP Datasheet(PDF) 33 Page - ELAN Microelectronics Corp

EM78P458AP Datasheet(HTML) 33 Page - ELAN Microelectronics Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

Datasheet Download

Link URL