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IO10PDB0V0 Datasheet(PDF) 177 Page - Microsemi Corporation |
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IO10PDB0V0 Datasheet(HTML) 177 Page - Microsemi Corporation |
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177 / 197 page ![]() SmartFusion Customizable System-on-Chip (cSoC) Re vi s i on 12 5 - 63 P11 GND GND P12 VCC VCC P13 GND GND P14 VCC VCC P15 GND GND P16 VCCFPGAIOB1 VCCFPGAIOB1 P17 TDI TDI P18 TCK TCK P19 GND GND P20 TMS TMS P21 TDO TDO P22 TRSTB TRSTB R1 MSS_RESET_N MSS_RESET_N R2 VCCFPGAIOB5 VCCFPGAIOB5 R3 GPIO_1/IO46RSB4V0 GPIO_1/IO55RSB4V0 R4 NC NC R5 NC NC R6 NC NC R7 NC NC R8 GND GND R9 VCC VCC R10 GND GND R11 VCC VCC R12 GND GND R13 VCC VCC R14 GND GND R15 VCC VCC R16 JTAGSEL JTAGSEL R17 NC NC R18 NC NC R19 NC NC R20 NC NC R21 VCCFPGAIOB1 VCCFPGAIOB1 R22 NC NC Pin Number FG484 A2F200 Function A2F500 Function Notes: 1. Shading denotes pins that do not have completely identical functions from density to density. For example, the bank assignment can be different for an I/O, or the function might be available only on a larger density device. 2. *: Indicates that the signal assigned to the pins as a CLKBUF/CLKBUF_LVPECL/CLKBUF_LVDS goes through a glitchless mux. In order for the glitchless mux to operate correctly, the signal must be a free-running clock signal. Refer to the ’Glitchless MUX’ section in the SmartFusion Microcontroller Subsystem User’s Guide for more details. |
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