PICASO datasheet(11/24 Pages) ETC2

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4D SYSTEMS

PICASO Processor

Page 11 of 23

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the IO4/BUS_RD or IO5/BUS_WR for read or write

respectively. For detailed usage refer to the

separate document titled:

'PICASO-4DGL-Internal-Functions.pdf'.

IO1-IO3 pins (3 x GPIO pins):

General purpose I/O pins. Each pin can be

individually set for INPUT or an OUTPUT. Power-

Up Reset default is all INPUTS.

IO4/BUS_RD pin (GPIO IO4 or BUS_RD pin):

General Purpose IO4 pin. Also used for BUS_RD

signal to read and latch the data in to the parallel

GPIO BUS0..BUS7.

IO5/BUS_WR pin (GPIO IO5 or BUS_WR pin):

General Purpose IO5 pin. Also used for BUS_WR

signal to write and latch the data to the parallel

GPIO BUS0..BUS7.

BUS0-BUS7 pins (GPIO 8-Bit Bus):

8-bit parallel General purpose I/O Bus.

Note: All GPIO pins are 5.0V tolerant.

System Pins

5.7.

VCC pins (Device Supply Voltage):

Device supply voltage pins. These pins must be

connected to a regulated supply voltage in the

range of 3.0 Volts to 3.6 Volts DC. Nominal

operating voltage is 3.3 Volts.

GND pins (Device Ground):

Device ground pins. These pins must be connected

to system ground.

RESET pin (Device Master Reset):

Device Master Reset pin. An active low pulse of

greater than 2 micro-seconds will reset the device.

Connect a resistor (1K through to 10K, nominal

4.7K) from this pin to VCC. Only use open collector

type circuits to reset the device if an external reset

is required. This pin is not driven low by any

internal conditions.

CLK1, CLK2 pins (Device Oscillator Inputs):

CLK1 and CLK2 are the device oscillator pins.

Connect a 12MHz AT strip cut crystal with 22pF

capacitors from each pin to GND as shown in the

diagram below.

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