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MAX20021 Datasheet(PDF) 13 Page - Maxim Integrated Products |
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MAX20021 Datasheet(HTML) 13 Page - Maxim Integrated Products |
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13 / 16 page ![]() MAX20021/MAX20022 Automotive Quad, Low-Voltage Step-Down DC-DC Converters www.maximintegrated.com Maxim Integrated │ 13 The external feedback resistive divider must be frequency compensated for proper operation. Place a capacitor across R1 in the resistive divider network. Use the follow- ing equation to determine the value of the capacitor: R2 R2 If 1, C1 C R1 R1 else C1 C, where C 15pF > = = = Connect OUTS_ to VOUT_ for a fixed 1.0V output voltage. Inductor Selection The PMICs are optimized for use with a 1.5µH inductor for 2.2MHz and 3.2MHz operation. Chip inductors can be used for additional board-space savings. Input Capacitor The PMICs are designed to operate with a single 2.2µF ceramic bypass capacitor on each PV_ input. Phase interleaving of the four buck converters contributes to a lower required input capacitance by canceling input ripple currents. Place the bypass capacitors as close as possible to their corresponding PV_ input to ensure the best EMI and jitter performance. Output Capacitor All outputs of the PMICs are optimized for use with a 10FF X7R ceramic capacitor. Additional output capacitance can be used if better voltage ripple or load transient response is required. Due to the soft-start sequence, the device is unable to drive arbitrarily large output capacitors. Thermal Considerations How much power the package can dissipate strongly depends on the mounting method of the IC to the PCB and the copper area for cooling. Using the JEDEC test standard, the maximum power dissipation allowed is 2285mW in the TQFN package. More power dissipation can be handled by the package if great attention is given during PCB layout. For example, using the top and bottom copper as a heatsink and connecting the thermal vias to one of the middle layers (GND) transfers the heat from the package into the board more efficiently, resulting in lower junction temperature at high power dissipation in some PMIC applications. Furthermore, the solder mask around the IC area on both top and bottom layers can be removed to radiate the heat directly into the air. The maximum allowable power dissipation in the IC is as follows: ( ) J(MAX) A MAX JC CA TT P − = θ + θ where TJ(MAX) is the maximum junction temperature (+150ºC), TA is the ambient air temperature, BJC (3ºC/W for the 28-pin TQFN) is the thermal resistance from the junctiontothecase,andθCA is the thermal resistance from the case to the surrounding air through the PCB, copper traces,andthepackagematerials.θCA is directly related to system-level variables and can be modified to increase the maximum power dissipation. The TQFN package has an exposed thermal pad on its underside. This pad provides a low thermal-resistance path for heat transfer into the PCB. This low thermally resistive path carries a majority of the heat away from the IC. The PCB is effectively a heatsink for the IC. The exposed pad should be connected to a large ground plane for proper thermal and electrical performance. The minimum size of the ground plane is dependent upon many system vari- ables. To create an efficient path, the exposed pad should be soldered to a thermal landing, which is connected to the ground plane by thermal vias. The thermal landing should be at least as large as the exposed pad and can be made larger depending on the amount of free space from the exposed pad to the other pin landings. A sample lay- out is available on the MAX20022 evaluation kit to speed designs. PCB Layout Guidelines Careful PCB layout is critical to achieve low switching losses and clean, stable operation. Use a multilayer board whenever possible for better noise immunity and power dissipation. Follow these guidelines for good PCB layout: 1) Use a large contiguous copper plane under the PMIC packages. Ensure that all heat-dissipating components have adequate cooling. 2) Keep the high-current paths short, especially at the ground terminals. This practice is essential for stable, jitter–free operation. The high current path comprising of input capacitor, inductor, and the output capacitor should be as short as possible. Figure 5. Adjustable Output-Voltage Configuration MAX20022 VOUT_ R1 C1 OUTS_ R2 |
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