HT47C20L datasheet(24/55 Pages) HOLTEK

24 / 55 page

HT47C20L

January 18, 2000

Label

(ADCR)

Bits

Function

OVB/OVA

In the RC type A/D converter mode, this bit is used to define the timer/event

counter interrupt which comes from timer A overflow or timer B overflow.

(0= timer A overflow; 1= timer B overflow)

In the timer/event counter mode, this bit is void.

ADC/TM

To define 16-bit timer/event counter or RC type A/D converter is enable.

(0= timer/event counter enable; 1= A/D converter is enable)

2~3 Unused bits, read as ²0²

To define the A/D converter operating mode (M3, M2, M1, M0)

0000= IN0 external clock input mode

0001= RS0~CS0 oscillation (reference resistor and reference capacitor)

0010= RT0~CS0 oscillation (resistor sensor and reference capacitor)

0011= CRT0~CS0 oscillation (resistor sensor and reference capacitor)

0100= RS0~CRT0 oscillation (reference resistor and sensor capacitor)

0101= RS1~CS1 oscillation (reference resistor and reference capacitor)

0110= RT1~CS1 oscillation (resistor sensor and reference capacitor)

0111= IN1 external clock input mode

1XXX= Undefined mode

ADCR register

A/D converter

Two channels of RC type A/D converter are im-

plemented in the HT47C20L. The A/D con-

verter contains two 16-bit programmable

count-up counter and the timer A clock source

may come from the system clock, T1 (system

clock/4) or real time clock output. The timer B

clock source may come from the external RC os-

cillator. The TMRAL, TMRAH, TMRBL,

TMRBH are composed of the A/D converter when

ADC/TM bit (bit 1 of ADCR register) is ²1².

The A/D converter timer B clock source may

come from channel 0 (IN0 external clock input

mode, RS0~CS0 oscillation, RT0~CS0 oscilla-

tion, CRT0~CS0 oscillation (CRT0 is a resis-

tor), or RS0~CRT0 oscillation (CRT0 is a

capacitor) or channel 1 (RS1~CS1 oscillation,

RT1~CS1 oscillation or IN1 external clock in-

put). The timer A clock source is from the sys-

tem clock, T1 or real time clock prescaler clock

output decided by TMRC register.

There are six registers related to A/D converter,

i.e., TMRAH, TMRAL, TMRC, TMRBH, TMRBL

and ADCR. The internal timer clock is input to

TMRAH and TMRAL, the A/D clock is input to

TMRBH and TMRBL. The OVB/OVA bit (bit 0

of the ADCR register) decides whether timer A

overflows or timer B overflows, then the TF bit

is set and timer interrupt occurs. When the A/D

converter mode timer A or timer B overflows,

the TON bit is reset and stop counting. Writing

TMRAH/TMRBH puts the starting value in the

timer A/timer B and reading TMRAH/TMRBH

gets the contents of the timer A/timer B. Writ-

ing TMRAL/TMRBL only writes the data into a

low byte buffer, and writing TMRAH/TMRBH

will write the data and the contents of the low

byte buffer into the timer A/timer B (16-bit) si-

multaneously. The timer A/timer B is change by

writing TMRAH/TMRBH operations and writing

TMRAL/TMRBL will keep the timer A/timer B

unchanged.

Reading TMRAH/TMRBH will also latch the

TMRAL/TMRBL into the low byte buffer to

avoid the false timing problem. Reading

TMRAL/TMRBL returns the contents of the

low byte buffer. In other word, the low byte of

timer A/timer B can not be read directly. It

must read the TMRAH/TMRBH first to make

the low byte contents of timer A/timer B be

latched into the buffer.

HT47C20L Datasheet(PDF) 24 Page - Holtek Semiconductor Inc

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