GMS87C1102 datasheet(60/89 Pages) HYNIX

60 / 89 page

GMS81C1102 / GMS81C1202

Jan. 2002 ver 2.0

19. INTERRUPTS

The GMS81C1202 interrupt circuits consist of Interrupt

enable register (IENH, IENL), Interrupt request flags of

IRQH, IRQL, Interrupt Edge Selection Register (IEDS),

priority circuit and Master enable flag("I" flag of PSW).

The configuration of interrupt circuit is shown in Figure

19-1 and Interrupt priority is shown in Table 19-1 .

The External Interrupts INT0 and INT1 can each be transi-

tion-activated (1-to-0, 0-to-1 and both transiton).

The flags that actually generate these interrupts are bit

INT0IFand INT1IF in Register IRQH. When an external

interrupt is generated, the flag that generated it is cleared

by the hardware when the service routine is vectored to

only if the interrupt was transition-activated.

The Timer 0 and Timer 1 Interrupts are generated by T0IF,

T1IF, which are set by a match in their respective timer/

counter register. The AD converter Interrupt is generated

by ADIF which is set by finishing the analog to digital con-

version. The Watch dog timer Interrupt is generated by

WDTIF which set by a match in Watch dog timer register

( when the bit WDTON is set to "0"). The Basic Interval

Timer Interrupt is generated by BITIF which is set by a

overflowing of the Basic Interval Timer Register(BITR).

Figure 19-1 Block Diagram of Interrupt Function

The interrupts are controlled by the interrupt master enable

flag I-flag (bit 2 of PSW), the interrupt enable register

(IENH, IENL) and the interrupt request flags (in IRQH,

IRQL) except Power-on reset and software BRK interrupt.

Interrupt enable registers are shown in Figure 19-2 . These

registers are composed of interrupt enable flags of each in-

terrupt source, these flags determines whether an interrupt

will be accepted or not. When enable flag is "0", a corre-

sponding interrupt source is prohibited. Note that PSW

contains also a master enable bit, I-flag, which disables all

interrupts at once.

BIT

BITIF

WDTIF

WDT

A/D Converter

Timer 1

Timer 0

External Int. 1

External Int. 0

IENH

Interrupt Enable

IRQH

IRQL

Interrupt

Vector

Address

Generator

Internal bus line

Release STOP

To CPU

Interrupt Master

Enable Flag

I Flag

IENL

I-flag is in PSW, it is cleared by “DI”, set by

“EI” instruction.When it goes interrupt service,

I-flag is cleared by hardware, thus any other

interrupt are inhibited. When interrupt service is

completed by “RETI” instruction, I-flag is set to

“1” by hardware.

INT0IF

INT1IF

T0IF

T1IF

ADIF

IEDS

Reset/Interrupt

Symbol

Priority

Vector Addr.

Hardware Reset

External Interrupt 0

External Interrupt 1

Timer 0

Timer 1

A/D Converter

Watch Dog Timer

Basic Interval Timer

RESET

INT0

INT1

Timer 0

Timer 1

A/D C

WDT

BIT

FFFEH

FFFAH

FFF8H

FFF6H

FFF4H

FFEAH

FFE8H

FFE6H

Table 19-1 Interrupt Priority

GMS87C1102 Datasheet(PDF) 60 Page - Hynix Semiconductor

GMS87C1102 Datasheet(HTML) 60 Page - Hynix Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89

Datasheet Download

Link URL