GMS87C1102 datasheet(69/89 Pages) HYNIX

69 / 89 page

GMS81C1102 / GMS81C1202

Jan. 2002 ver 2.0

21.3 Internal RC-Oscillated Watchdog Timer Mode

In the Internal RC-Oscillated Watchdog Timer mode, the

on-chip oscillator is stopped. But internal RC oscillation

circuit is oscillated in this mode. The on-chip RAM and

Control registers are held. The port pins out the values held

by their respective port data register, port direction regis-

ters.

The Internal RC-Oscillated Watchdog Timer mode is

activated by execution of STOP instruction after set-

ting the bit WAKEUP and RCWDT of CKCTLR to

“01”. (This register should be written by byte opera-

tion. If this register is set by bit manipulation instruc-

tion, for example “set1” or “clr1” instruction, it may be

undesired operation)

Note: After STOP instruction, at least two or more NOP in-

struction should be written

Ex)

LDM

WDTR,#1111_1111B

LDM

CKCTLR,#0010_1110B

LDM

IRQH,#0

LDM

IRQL,#0

STOP

NOP

Release the Internal RC-Oscillated Watchdog Timer mode

The exit from Internal RC-Oscillated Watchdog Timer

mode is hardware reset or external interrupt. Reset re-de-

fines all the Control registers but does not change the on-

chip RAM. External interrupts allow both on-chip RAM

and Control registers to retain their values.

If I-flag = 1, the normal interrupt response takes place. In

this case, if the bit WDTON of CKCTLR is set to “0” and

the bit WDTE of IENH is set to “1”, the device will exe-

cute the watchdog timer interrupt service routine.(Figure

21-5) However, if the bit WDTON of CKCTLR is set to

“1”, the device will generate the internal RESET signal

and execute the reset processing. (Figure 21-6)

If I-flag = 0, the chip will resume execution starting with

the instruction following the STOP instruction. It will not

vector to interrupt service routine (refer to Figure 21-1).

When exit from Internal RC-Oscillated Watchdog Timer

mode by external interrupt, the oscillation stabilization

time is required for normal operation. Figure 21-5 shows

the timing diagram. When release the Internal RC-Oscil-

lated Watchdog Timer mode, the basic interval timer is ac-

tivated on wake-up. It is increased from 00H until FFH. The

count overflow is set to start normal operation. Therefore,

before STOP instruction, user must be set its relevant pres-

caler divide ratio to have long enough time (more than

20msec). This guarantees that oscillator has started and

stabilized.

By reset, exit from internal RC-Oscillated Watchdog Tim-

er mode is shown in Figure 21-6.

Figure 21-5 Internal RCWDT Mode Releasing by External Interrupt or WDT Interrupt

RCWDT Mode

Normal Operation

Oscillator

(XIN pin)

N+1

N+2

N-1

N-2

Clear Basic Interval Timer

STOP Instruction Execution

Normal Operation

Stabilization Time

tST > 20mS

Internal

Clock

External

Interrupt

BIT

Counter

Internal

RC Clock

(or WDT Interrupt)

GMS87C1102 Datasheet(PDF) 69 Page - Hynix Semiconductor

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