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GMS81C2012K Datasheet(PDF) 34 Page - Hynix Semiconductor |
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GMS81C2012K Datasheet(HTML) 34 Page - Hynix Semiconductor |
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34 / 107 page ![]() GMS81C2012/GMS81C2020 HYUNDAI MicroElectronics 34 MAR. 2000 Ver 1.00 ECH BITR1 Basic Interval Timer Data Register ECH CKCTLR1 - WAKEUP RCWDT WDTON BTCL BTS2 BTS1 BTS0 EDH WDTR WDTCL 7-bit Watchdog Counter Register EFH PFDR2 -- -- - PFDIS PFDM PFDS F4H R0FUNC - - - - BUZO EC0 INT1 INT0 F5H R4FUNC - - - - - - - T0O F6H R5FUNC - PWM1O/ T1O - - - - - - F7H R6FUNC AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 F8H R7FUNC - - - - AN11 AN10 AN9 AN8 F9H R5NODR NODR7 NODR6 NODR5 NODR4 NODR3 NODR2 NODR1 NODR0 FAH SCMR - - - CS1 CS0 SUBOFF CLKSEL MAINOFF FBH RA - -- --- - RA0 1.The register BITR and CKCTLR are located at same address. Address ECH is read as BITR, written to CKCTLR. 2.The register PFDR only be implemented on devices, not on In-circuit Emulator. Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Table 8-3 Control Registers of GMS81C2020 These registers of shaded area can not be access by bit manipulation instruction as " SET1, CLR1 ", but should be access by reg- ister operation instruction as " LDM dp,#imm ". |
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