HDM8515P datasheet(4/75 Pages) HYNIX

4 / 75 page

TABLE OF CONTENTS

1. INTRODUCTION TO THE HDM8515...................................................................................................................7

1.1 FEATURES AND BENEFITS..................................................................................................................................8

2. HARDWARE SPECIFICATION..............................................................................................................................9

3. TECHNICAL OVERVIEW..................................................................................................................................... 19

3.1 DUAL CHANNEL ANALOG TO DIGITAL CONVERTER .................................................................................. 19

3.2 VARIABLE RATE DEMODULATOR.................................................................................................................. 21

3.3 NOISE MEASUREMENT CIRCUIT .....................................................................................................................23

3.4 VITERBI DECODER.............................................................................................................................................25

3.5 AUTONOMOUS ACQUISITION..........................................................................................................................26

3.6 REED SOLOMON DECODER.............................................................................................................................. 28

3.7 CLOCK GENERATION PLL .................................................................................................................................30

3.8 DBS RECEIVER................................................................................................................................................... 35

3.9 DISEQC INTERFACE ...........................................................................................................................................36

4. MECHANICAL SPECIFICATIONS..................................................................................................................... 37

4.1 100 PIN QUAD FLAT PACK................................................................................................................................37

4.2 64 PIN THIN QUAD FLAT PACK........................................................................................................................39

4.3 RECOMMENDED ANALOG PIN CONNECTION............................................................................................... 41

4.4 RECOMMENDED CLOCK GENERATION CIRCUIT...........................................................................................41

5. SIGNAL DESCRIPTION....................................................................................................................................... 42

5.1 INPUTS..................................................................................................................................................................42

5.2 OUTPUTS............................................................................................................................................................. 42

5.3 M ONIT OR AND CONTROL INTERFACE ...........................................................................................................45

5.4 I2C MODE............................................................................................................................................................. 46

6. REGISTER DEFINITIONS..................................................................................................................................... 48

6.1 W RITE REGISTERS..............................................................................................................................................48

6.2 READ REGISTERS................................................................................................................................................61

APPENDIX.................................................................................................................................................................... 66

A1. LOOP FILTER PROGRAMMING APPLICATION NOTE................................................................................67

A2. FALSE LOCK ESCAPE APPLICATION NOTE .................................................................................................70

A3. PERFORMANCE WITH INTERFERENCE.......................................................................................................... 71

A4. NYQUIST CRITERIA CONSIDERATIONS......................................................................................................... 75

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