HDM8515P datasheet(7/75 Pages) HYNIX

7 / 75 page

1. Introduction to the HDM8515

The HDM8515 digital demodulator for direct broadcast satellite receivers is a single chip solution fully

compliant with the European Telecommunications Standards Institute (ETSI) specification ETS 300

421. This chip integrates an A/D converter, a variable rate matched filter, a variable rate QPSK

demodulator with a Viterbi decoder, a deinterleaver and a Reed Solomon decoder.

The HDM8515, which is implemented in a 0.25 micron CMOS, Four Layer Metal Process, provides

variable rate capability while operating with a fixed frequency sampling clock. Digital samples of

baseband I and Q data are generated by an internal A/D converter, then provided to the demodulator at

a fixed sample rate. The root raised cosine filter is implemented internally with fully digital techniques.

Similarly, the symbol timing recovery and carrier phase tracking functions are performed entirely in the

digital domain. This approach provides minimum constraints on external circ uits, thus reducing overall

system costs.

The HDM8515 may be configured by an external processor for a specific symbol rate, and carrier

frequency along with loop gain parameters. The HDM8515 provides an external AGC signal which is

used to control the gain of the analog signal which is applied to the down-converters. And it also

provides a digital AGC internally which controls the gain of the signal out of the matched filters. In

addition, the HDM8515 provides fully programmable sweep circuitry to aid in initial acquisition when

large frequency offsets may be present.

The digital frequency translation capability of the HDM8515 permits this part to be used in frequency

multiplexing applications. In this application, an entire transponder bandwidth containing many signals

is sampled at a fixed rate. The digital oscillator within the HDM8515 is programmed to the specific

desired carrier frequency within that band to permit the selected signal to be passed through the

baseband filter and processed by the demodulator circuits.

FIGURE 1: TOP LEVEL BLOCK DIAGRAM

Variable

Rate

QPSK

Demodulator

Viterbi

Decoder

Synchronizatio n

and

Deinterleaving

Reed

Solomon

Decoder

Data Clock

Data

QPSK

Lock

Node

Sync

Symbol Clock

Viterbi Bit Clock

Frame

Sync

Viterbi

Data

A/D

Converter

I2C

DiSEqC

Interface

MCU

Interface

BER

Monitoring

PLL

C/N

Estimator

Byte Sync

QPSK Lock

AIN_I

AIN_Q

WB_AGC

DISEQC

SCL_I2C

SDA_I2C

HI_ADDR[5:0]

HI_DATA[7:0]

XTAL1_IN

DATA_CLK

DATA[7:0]

QPSK_LOCK

FRAME_SYNC

Reference clk

AGC

AGC_Detector

HDM8515P Datasheet(PDF) 7 Page - Hynix Semiconductor

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