28F002BC datasheet(21/37 Pages) INTEL

21 / 37 page

28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY

PRELIMINARY

SR.7 =

Start

Write 20H and

Block Address

Write D0H and

Block Address

Full Status

Check if Desired

Block Erase

Complete

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (See Above)

Read Status Register

Range Error

Suspend

Erase

Suspend Erase

Loop

Yes

Command Sequence

Error

SR.3 =

SR.5 =

SR.4,5 =

Block Erase

Error

Bus

Operation

Command

Comments

Standby

Check SR.4,5

Both 1 = Command

Sequence Error

Standby

SR.3 MUST be cleared, if set during an erase attempt, before further

attempts are allowed by the Write State Machine.

SR.5 is only cleared by the Clear Status Register command, in

cases where multiple blocks are erase before full status is checked.

If error is detected, clear the status register before attempting

retry or other error recovery.

Check SR.5

1 = Block Erase Error

Standby

Bus

Operation

Command

Comments

Write

Erase Setup

Read

Data = 20H

Addr = Within Block to Be Erased

Check SR.7

1 = WSM Ready

0 = WSM Busy

Repeat for subsequent block erasures.

Full Status Check can be done after each block erase, or after a

sequence of block erasures.

Write FFH after the last operation to reset device to read array mode.

Status Register Data

Toggle CE# or OE# to Update

Status Register

Standby

Erase

Confirm

Data = D0H

Addr = Within Block to Be Erased

Block Erase

Successful

Check SR.3

1 = V

Low Detect

0578_07

Figure 8. Automated Block Erase Flowchart

28F002BC Datasheet(PDF) 21 Page - Intel Corporation

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