28F008C3 datasheet(42/59 Pages) INTEL

42 / 59 page

3 VOLT ADVANCED+ BOOT BLOCK

PRODUCT PREVIEW

Start

Write 20H

Write D0H and

Block Address

Read Status Register

SR.7 =

Full Status

Check if Desired

Block Erase Complete

FULL STATUS CHECK PROCEDURE

Bus Operation

Write

Standby

Repeat for subsequent block erasures.

Full Status Check can be done after each block erase or after a sequence of

block erasures.

Write FFH after the last write operation to reset device to read array mode.

Bus Operation

Standby

SR. 1 and 3 MUST be cleared, if set during an erase attempt, before further

attempts are allowed by the Write State Machine.

SR.1, 3, 4, 5 are only cleared by the Clear Staus Register Command, in cases

where multiple bytes are erased before full status is checked.

If an error is detected, clear the status register before attempting retry or other

error recovery.

Yes

Suspend Erase

Suspend

Erase Loop

Standby

Command

Erase Setup

Erase Confirm

Comments

Data = 20H

Addr = Within Block to Be

Erased

Data = D0H

Addr = Within Block to Be

Erased

Check SR.7

1 = WSM Ready

0 = WSM Busy

Command

Comments

Check SR.3

1 = V

PP Low Detect

Check SR.4,5

Both 1 = Command Sequence

Error

Read Status Register

Data (See Above)

PP Range Error

Command Sequence

Error

Block Erase

Successful

SR.3 =

SR.4,5 =

Block Erase Error

SR.5 =

Attempted Erase of

Locked Block - Aborted

SR.1 =

Read

Status Register Data Toggle

CE# or OE# to Update Status

Standby

Check SR.5

1 = Block Erase Error

Standby

Check SR.1

1 = Attempted Erase of

Locked Block - Erase Aborted

Figure 14. Automated Block Erase Flowchart

28F008C3 Datasheet(PDF) 42 Page - Intel Corporation

28F008C3 Datasheet(HTML) 42 Page - Intel Corporation

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