AD5060 datasheet(15/24 Pages) AD

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AD5040/AD5060

Rev. A | Page 15 of 24

THEORY OF OPERATION

The AD5040/AD5060 are single 14-/16-bit, serial input, voltage

output DACs. The parts operate from supply voltages of 2.7 V

to 5.5 V. Data is written to the AD5060 in a 24-bit word format,

and to the AD5040 in a 16-bit word format, via a 3-wire serial

interface.

Both the AD5040 and AD5060 incorporate a power-on reset

circuit that ensures the DAC output powers up to a known out-

put state (midscale or zero-scale, see the Ordering Guide). The

devices also have a software power-down mode that reduces the

typical current consumption to less than 1 μa.

DAC ARCHITECTURE

The DAC architecture of the AD5060 consists of two matched

DAC sections. A simplified circuit diagram is shown in

Figure 40. The 4 MSBs of the 16-bit data-word are decoded to

drive 15 switches, E1 to E15. Each of these switches connects

1 of 15 matched resistors to either DACGND or the VREF

buffer

output. The remaining 12 bits of the data-word drive switches

S0 to S11 of a 12-bit voltage mode R-2R ladder network.

VREF

S11

E15

VOUT

12-BIT R-2R LADDER

FOUR MSBs DECODED INTO

15 EQUAL SEGMENTS

Figure 40. AD5060 DAC Ladder Structure

REFERENCE BUFFER

The AD5040 andAD5060 operate with an external reference.

The reference input (VREF) has an input range of 2 V to

VDD − 50 mV. This input voltage is then used to provide a

buffered reference for the DAC core.

SERIAL INTERFACE

The AD5060/AD5040 have a 3-wire serial interface (SYNC,

SCLK, and DIN), which is compatible with SPI, QSPI, and

MICROWIRE interface standards, as well as most DSPs.

shows a timing diagram of a typical AD5060 write

sequence.

Figure 2

The write sequence begins by bringing the SYNC line low. For

the AD5060, data from the DIN line is clocked into the 24-bit

shift register on the falling edge of SCLK. The serial clock

frequency can be as high as 30 MHz, making these parts

compatible with high speed DSPs. On the 24th falling clock

edge, the last data bit is clocked in and the programmed

function is executed (that is, a change in the DAC output or a

change in the mode of operation).

At this stage, the SYNC line can be kept low or be brought

high. In either case, it must be brought high for a minimum of

12 ns before the next write sequence so that a falling edge of

SYNC can initiate the next write sequence. Because the SYNC

buffer draws more current when VIH = 1.8 V than it does when

VIH = 0.8 V, SYNC should be idled low between write sequences

for an even lower power operation of the part. As previously

indicated, however, it must be brought high again just before

the next write sequence. The AD5040 requires 16 clock periods

to update the input shift register. On the 16th falling clock edge,

the last data bit is clocked in and the programmed function is

executed (that is, a change in the DAC output or a change in the

mode of operation).

Input Shift Register

The AD5060 input shift register is 24 bits wide; see Figure 41.

PD1 and PD0 are control bits that control the operating mode

of the part—normal mode or any one of three power-down

modes (see the Power-Down Modes section for more detail).

The next 16 bits are the data bits. These are transferred to the

DAC register on the 24th falling edge of SCLK.

DATA BITS

DB15 (MSB)

DB0 (LSB)

D15

D14

D13

D12

D11

D10

NORMAL OPERATION

Ω TO GND

100k

Ω TO GND

3-STATE

POWER-DOWN MODES

PD1

PD0

Figure 41. AD5060 Input Register Content

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