80960CF-30 datasheet(9/62 Pages) INTEL

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SPECIAL ENVIRONMENT 80960CF-30 -25 -16

Table 2 80960CF Pin DescriptionExternal Bus Signals

Name

Type

Description

A312

ADDRESS BUS

carries the physical address upper 30 bits A31 is the most

significant address bit and A2 is the least significant During a bus access A312

identify all external addresses to word (4-byte) boundaries The byte enable

H(Z)

signals indicate the selected byte in each word During burst accesses A3 and A2

R(Z)

increment to indicate successive data cycles

D310

DATA BUS

carries 32- 16- or 8-bit data quantities depending on bus width

configuration The least significant bit of the data is carried on D0 and the most

S(L)

significant on D31 When the bus is configured for 8-bit data the lower 8 data

H(Z)

lines D70 are used For 16-bit bus widths D150 are used For 32-bit bus widths

R(Z)

the full data bus is used

BE3

BYTE ENABLES

select which of the four bytes addressed by A312 are active

during an access to a memory region configured for a 32-bit data-bus width BE3

BE2

applies to D3124 BE2 applies to D2316 BE1 applies to D158 and BE0 applies

BE1

H(Z)

to D70

BE0

R(1)

32-bit bus

BE3

– Byte Enable 3

– enable D3124

BE2

– Byte Enable 2

– enable D2316

BE1

– Byte Enable 1

– enable D158

BE0

– Byte Enable 0

– enable D70

For accesses to a memory region configured for a 16-bit data-bus width the

processor directly encodes BE3 BE1 and BE0 to provided BHE A1 and BLE

respectively

16-bit bus

BE3

– Byte High Enable (BHE)

– enable D158

BE2

– Not used (is driven high or low)

BE1

– Address Bit 1 (A1)

BE0

– Byte Low Enable (BLE)

– enable D70

For accesses to a memory region configured for an 8-bit data bus width the

processor directly encodes BE1 and BE0 to provide A1 and A0 respectively

8-bit bus

BE3

– Not used (is driven high or low)

BE2

– Not used (is driven high or low)

BE1

– Address Bit 1 (A1)

BE0

– Address Bit 0 (A0)

WRITEREAD

is asserted for read requests and deasserted for write requests

The WR signal changes in the same clock cycle as ADS It remains valid for the

entire access in non-pipelined regions In pipelined regions WR is not

H(Z)

guaranteed valid in the last cycle of a read access

R(0)

ADS

ADDRESS STROBE

indicates valid address and the start of a new bus access

ADS is asserted for the first clock of a bus access

H(Z)

R(1)

READY

is an input which signals the termination of a data transfer READY is

used to indicate that read data on the bus is valid or that a write-data transfer has

S(L)

completed The READY signal works in conjunction with the internally

H(Z)

programmed wait-state generator If READY is enabled in a region the pin is

R(Z)

sampled after the programmed number of wait-states has expired If the READY

pin is deasserted wait states continue to be inserted until READY becomes

asserted This is true for the NRAD NRDD NWAD and NWDD wait states The

NXDA wait states cannot be extended

80960CF-30 Datasheet(PDF) 9 Page - Intel Corporation

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