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80960CF-33 Datasheet(PDF) 53 Page - Intel Corporation |
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80960CF-33 Datasheet(HTML) 53 Page - Intel Corporation |
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53 / 77 page  PRELIMINARY 47 A 80960CF-40, -33, -25, -16 Figure 23. Clock Synchronization in the 2-x Clock Mode Figure 24. Clock Synchronization in the 1-x Clock Mode CLKIN RESET PCLK2:1 (Case 1) PCLK2:1 (Case 2) 1.5 V TIH TIS 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V TCP Max Min TCP Max Min TCP SYNC Note: Case 1 and Case 2 show two possible polarities of PCLK2:1 Min 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V F_CX024A Max CLKIN 1.5 V 1.5 V RESET TIH TIS 1.5 V 2x CLK Note: In 1x clock mode, the RESET pin is actually sampled on the falling edge of 2xCLK. 2xCLK is an internal signal generated by the PLL and is not available on an external pin. Therefore, RESET is specified relative to the rising edge of CLKIN. The RESET pin is sampled when PCLK is high. F_CX025A |
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