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80960CF-33 Datasheet(PDF) 67 Page - Intel Corporation |
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80960CF-33 Datasheet(HTML) 67 Page - Intel Corporation |
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67 / 77 page ![]() PRELIMINARY 61 A 80960CF-40, -33, -25, -16 Figure 38. Burst, Pipelined Read Request With Wait States, 16-Bit Bus ADS A31:4, SUP, DMA, D/C, BE0/BLE, W/R A3:2 BE1/A1 WAIT BLAST DT/R DEN PCLK Byte Order Bus Width NWDD NWAD NXDA NRDD NRAD Pipe- Lining External Ready Control Burst 31-23 22 18-17 21 20-19 16-12 7-3 11-10 9-8 2 1 0 X x 0 0 X xx 16-bit 01 X xx X xxxxx 1 01 2 00010 ON 1 Enabled 1 0 0..0 Disabled 0 Function Bit Value D15:0 A1=0 D15:0 A1=1 D15:0 A1=0 D15:0 A1=1 D15:0 D' A2 1 D 1 D 1 D 1 A' 2 1 D D' In- valid Non-pipelined request concludes, pipelined reads begin. Pipelined reads conclude, non-pipelined requests begin. A3:2 = 00 or 10 A3:2 = 01 or 11 Valid In- valid Valid In- valid BE3/BHE, D31:0 F_CX040A LOCK Valid Valid In- valid |
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