AD5380_15 datasheet(22/40 Pages) AD

22 / 40 page

AD5380

Data Sheet

FUNCTIONAL DESCRIPTION

DAC ARCHITECTURE—GENERAL

The AD5380 is a complete, single-supply, 40-channel voltage

output DAC that offers 14-bit resolution. The part is available

in a 100-lead LQFP package and features both a parallel and a

serial interface. This product includes an internal, software

selectable, 1.25 V/2.5 V, 10 ppm/°C reference that can be used

to drive the buffered reference inputs; alternatively, an external

reference can be used to drive these inputs. Internal/external

reference selection is via the CR10 bit in the control register;

CR12 selects the reference magnitude if the internal reference

is rail-to-rail output capable of driving 5 kΩ in parallel with a

200 pF load.

Figure 27. Single-Channel Architecture

The architecture of a single DAC channel consists of a 14-bit

resistor-string DAC followed by an output buffer amplifier

operating at a gain of 2. This resistor-string architecture guaran-

tees DAC monotonicity. The 14-bit binary digital code loaded

to the DAC register determines at what node on the string the

voltage is tapped off before being fed to the output amplifier.

Each channel on these devices contains independent offset and

gain control registers that allow the user to digitally trim offset

and gain. These registers give the user the ability to calibrate out

errors in the complete signal chain, including the DAC, using

the internal m and c registers, which hold the correction factors.

All channels are double buffered, allowing synchronous updat-

ing of all channels using the LDAC pin. Figure 27 shows a block

diagram of a single channel on the AD5380. The digital input

transfer function for each DAC can be represented as

x2 = [(m + 2)/ 2n× x1] + (c – 2n– 1)

where:

x2 is the data-word loaded to the resistor string DAC.

x1 is the 14-bit data-word written to the DAC input register.

m is the gain coefficient (default is 0x3FFE on the AD5380).

The gain coefficient is written to the 13 most significant bits

(DB13 to DB1) and the LSB (DB0) is zero.

n = DAC resolution (n = 14 for AD5380).

c is the14-bit offset coefficient (default is 0x2000).

The complete transfer function for these devices can be

represented as

VOUT = 2 × VREF × x2/2n

x2 is the data-word loaded to the resistor string DAC. VREF is

the internal reference voltage or the reference voltage externally

applied to the DAC REFOUT/REFIN pin. For specified

performance, an external reference voltage of 2.5 V is recom-

mended for the AD5380-5, and 1.25 V for the AD5380-3.

DATA DECODING

The AD5380 contains a 14-bit data bus, DB13 to DB0. Depend-

ing on the value of REG1 and REG0 (see Table 1), this data is

loaded into the addressed DAC input registers, offset (c)

registers, or gain (m) registers. The format data, offset (c), and

gain (m) register contents are shown in Table 10 to Table 12.

Table 9. Register Selection

REG1

REG0

Input Data Register (x1)

Offset Register (c)

Gain Register (m)

Special Function Registers (SFRs)

Table 10. DAC Data Format (REG1 = 1, REG0 = 1)

DB13 to DB0

DAC Output (V)

1111

2 VREF × (16383/16384)

1111

1110

2 VREF × (16382/16384)

0000

0001

2 VREF × (8193/16384)

0000

2 VREF × (8192/16384)

1111

2 VREF × (8191/16384)

0000

0001

2 VREF × (1/16384)

0000

Table 11. Offset Data Format (REG1 = 1, REG0 = 0)

DB13 to DB0

Offset (LSB)

1111

+8191

1111

1110

+8190

0000

0001

0000

1111

–1

0000

0001

–8191

0000

–8192

Table 12. Gain Data Format (REG1 = 0, REG0 = 1)

DB13 to DB0

Gain Factor

1111

1110

1111

1110

0.75

1111

1110

0.5

1111

1110

0.25

0000

VOUT

14-BIT

DAC

REG

m REG

c REG

×1 INPUT

REG

×2

INPUT DATA

VREF

AVDD

Rev. D | Page 22 of 40

AD5380 Datasheet(PDF) 22 Page - Analog Devices

AD5380 Datasheet(HTML) 22 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Datasheet Download

Link URL