ADE7754_15 datasheet(34/44 Pages) AD

34 / 44 page

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ADE7754

Table VIII. Register List (continued)

Address

Default

[A5:A0]

Name

R/W

Length

Value

Description

31h

CIrmsOS

R/W

Phase C Current RMS Offset Correction Register.

32h

AVrmsOS

R/W

Phase A Voltage RMS Offset Correction Register.

33h

BVrmsOS

R/W

Phase B Voltage RMS Offset Correction Register.

34h

CVrmsOS

R/W

Phase C Voltage RMS Offset Correction Register.

35h

AAPGAIN

R/W

Phase A Active Power Gain Adjust. The active power accumulation of the

Phase A can be calibrated by writing to this register. The calibration range

±50% of the nominal full scale of the active power. The resolution of the

gain is 0.0244%/LSB. See the Current Channel ADC Gain Adjust section.

36h

BAPGAIN

R/W

Phase B Active Power Gain Adjust.

37h

CAPGAIN

R/W

Phase C Active Power Gain Adjust.

38h

AVGAIN

R/W

Phase A Voltage RMS Gain. The apparent power accumulation of the

Phase A can be calibrated by writing to this register. The calibration

range is

±50% of the nominal full scale of the apparent power. The

resolution of the gain is 0.0244% / LSB. See the Voltage RMS Gain

Adjust section.

39h

BVGAIN

R/W

Phase B Voltage RMS Gain.

3Ah

CVGAIN

R/W

Phase C Voltage RMS Gain.

3Bh–

Reserved.

3Dh

3Eh

CHKSUM

Check Sum Register. The content of this register represents the sum of

all 1s of the latest register read from the SPI port.

3Fh

VERSION

Version of the Die.

*R/W: Read/Write capability of the register.

R: Read-only register.

R/W: Register that can be both read and written.

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