REV. 0

–40–

ADE7754

Interrupt Status Register (10h)/Reset Interrupt Status Register (11h)

The interrupt status register is used to determine the source of an interrupt event. When an interrupt event occurs in the ADE7754,

the corresponding flag in the interrupt status register is set logic high. The

IRQ pin will go active low if the corresponding bit in the

interrupt enable register is set logic high. When the MCU services the interrupt, it must first carry out a read from the interrupt sta-

tus register to determine the source of the interrupt. All the interrupts in the interrupt status register stay at their logic high state after

an event occurs. The state of the interrupt bit in the interrupt status register is reset to its default value once the reset interrupt status

register is read.

Table XVII. STATUS Register

Bit

Interrupt

Default

Event

Location

Flag

Value

Description

0

AEHF

0

Indicates that an interrupt was caused by the 0 to 1 transition of the MSB of the AENERGY

register (i.e., the AENERGY register is half full).

1

SAGA

0

Indicates that an interrupt was caused by a SAG on the line voltage of the Phase A.

2

SAGB

0

Indicates that an interrupt was caused by a SAG on the line voltage of the Phase B.

3

SAGC

0

Indicates that an interrupt was caused by a SAG on the line voltage of the Phase C.

4

ZXTOA

0

Indicates that an interrupt was caused by a missing zero crossing on the line voltage of the Phase A.

5

ZXTOB

0

Indicates that an interrupt was caused by a missing zero crossing on the line voltage of the Phase B.

6

ZXTOC

0

Indicates that an interrupt was caused by a missing zero crossing on the line voltage of the Phase C.

7

ZXA

0

Indicates a detection of rising zero crossing in the voltage channel of the Phase A.

8

ZXB

0

Indicates a detection of rising zero crossing in the voltage channel of the Phase B.

9

ZXC

0

Indicates a detection of rising zero crossing in the voltage channel of the Phase C.

Ah

LENERGY

0

In line energy accumulation, it indicates the end of an integration over an integer number of

half line cycles (LINCYC). See the Energy Calculation section.

Bh

RESET

0

Indicates that the ADE7754 has been reset.

Ch

PKV

0

Indicates that an interrupt was caused when the selected voltage input is above the value in the

PKVLV register.

Dh

PKI

0

Indicates that an interrupt was caused when the selected current input is above the value in the

PKILV register.

Eh

WFSM

0

Indicates that new data is present in the waveform register.

Fh

VAEHF

0

Indicates that an interrupt was caused by the 0 to 1 transition of the MSB of the VAENERGY

register (i.e., the VAENERGY register is half full).

0

0

0

0

0

0

0

0

F

E

D

C

B

A

9

8

INTERRUPT STATUS REGISTER*

0

0

0

0

0

0

0

0

7

6

5

4

3

2

1

0

VAEHF

(APPARENT ENERGY REGISTER HALF FULL)

PKI

(CURRENT CHANNEL PEAK DETECTION)

PKV

(VOLTAGE CHANNEL PEAK DETECTION)

AEHF

(ACTIVE ENERGY REGISTER HALF FULL)

SAG

(SAG EVENT DETECT)

ZX

(ZERO-CROSSING TIMEOUT DETECTION)

ZX

(ZERO-CROSSING DETECTION)

LENERGY

(END OF THE LAENERGY AND LVAENERGY ACCUMULATION)

WFSM

(NEW WAVEFORM SAMPLE READY)

ADDR: 10h

*REGISTER CONTENTS SHOW POWER-ON DEFAULTS

RESET