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W9812G2KB Datasheet(PDF) 39 Page - Winbond

Part # W9812G2KB
Description  1M X 4 BANKS X 32 BITS SDRAM
PDF  43 Pages
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Manufacturer  WINBOND [Winbond]
Direct Link  http://www.winbond.com
Logo WINBOND - Winbond

W9812G2KB Datasheet(HTML) 39 Page - Winbond

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W9812G2KB
Publication Release Date: Jun. 20, 2014
- 39 -
Revision: A01
11.19 Timing Chart of Burst Stop Cycle (Burst Stop Command)
11.20 Timing Chart of Burst Stop Cycle (Precharge Command)
0
1
11
10
9
8
7
6
5
4
3
2
(1) Read cycle
(a) CAS latency =2
Command
Q0
Q1
Q2
Q3
Q4
PRCG
Read
(b) CAS latency =3
Command
Q0
Q1
Q2
Q3
Q4
PRCG
Read
DQ
DQ
(2) Write cycle
Command
Q0
Q1
Q2
Q3
Q4
PRCG
Write
DQ
DQM
tWR
Read
BST
0
11
10
9
8
7
6
5
4
3
2
1
DQ
Q0
Q1
Q2
Q3
BST
( a ) CAS latency =2
C omma nd
( b )CAS latency = 3
(1) Read cycle
Q4
(2) Write cycle
C omma nd
Read
C omma nd
Q0
Q1
Q2
Q3
Q4
Q0
Q1
Q2
Q3
Q4
DQ
DQ
Write
BST
Note:
represents the Burst stop command
BST



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