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W9812G2KB Datasheet(PDF) 21 Page - Winbond

Part # W9812G2KB
Description  1M X 4 BANKS X 32 BITS SDRAM
PDF  43 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  WINBOND [Winbond]
Direct Link  http://www.winbond.com
Logo WINBOND - Winbond

W9812G2KB Datasheet(HTML) 21 Page - Winbond

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W9812G2KB
Publication Release Date: Jun. 20, 2014
- 21 -
Revision: A01
10.4 Mode Register Set Cycle
A0
A3
Addressing Mode
0
Sequential
1
Interleave
A0
A9
Single Write Mode
0
Burst read and Burst write
1
Burst read and single write
A0
A2
A1
A0
A0
0
0
0
A0
0
0
1
A0
0
1
0
A0
0
1
1
A0
1
0
0
A0
1
0
1
A0
1
1
0
A0
1
1
1
Burst Length
Sequential
Interleave
1
1
2
2
4
4
8
8
Reserved
Reserved
Full Page
CAS Latency
Reserved
Reserved
2
3
Reserved
A0
A6
A5
A4
A0
0
0
0
A0
0
1
0
A0
0
1
1
A0
1
0
0
A0
0
0
1
* "Reserved" should stay "0" during MRS cycle.
tRSC
tCMS
tCMH
tCMS
tCMH
tCMS
tCMH
tCMS
tCMH
tAS
tAH
CLK
CS
RAS
CAS
WE
A0-A11
BS0,1
Register
set data
next
command
A0
A1
A2
A3
A4
A5
A6
Burst Length
Addressing Mode
CAS Latency
(Test Mode)
A8
A0
A7
A9
A0
Write Mode
A10
BS0
A0
A11
"0"
"0"
"0"
"0"
"0"
Reserved
BS1
"0"
Reserved



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